10-22 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

10.6.2 

Determining IPI Destination

The destination of an IPI can be one, all, or a subset (group) of the processors on the system bus. The sender of 
the IPI specifies the destination of an IPI with the following APIC registers and fields within the registers:

•

ICR Register — The following fields in the ICR register are used to specify the destination of an IPI:
— Destination Mode — Selects one of two destination modes (physical or logical).
— Destination Field — In physical destination mode, used to specify the APIC ID of the destination 

processor; in logical destination mode, used to specify a message destination address (MDA) that can be 
used to select specific processors in clusters.

— Destination Shorthand — A quick method of specifying all processors, all excluding self, or self as the 

destination.

— Delivery mode, Lowest Priority — Architecturally specifies that a lowest-priority arbitration mechanism 

be used to select a destination processor from a specified group of processors. The ability of a processor to 
send a lowest priority IPI is model specific and should be avoided by BIOS and operating system software.

•

Local destination register (LDR) — Used in conjunction with the logical destination mode and MDAs to 
select the destination processors.

•

Destination format register (DFR) — Used in conjunction with the logical destination mode and MDAs to 
select the destination processors.

How the ICR, LDR, and DFR are used to select an IPI destination depends on the destination mode used: physical, 
logical, broadcast/self, or lowest-priority delivery mode. These destination modes are described in the following 
sections.
Determination of IPI destinations in x2APIC mode is discussed in Section 10.12.10.

10.6.2.1   Physical Destination Mode

In physical destination mode, the destination processor is specified by its local APIC ID (see Section 10.4.6, “Local 
APIC ID”). For Pentium 4 and Intel Xeon processors, either a single destination (local APIC IDs 00H through FEH) 
or a broadcast to all APICs (the APIC ID is FFH) may be specified in physical destination mode. 

All including Self

Valid

Edge

Fixed

X

All including Self

Valid

2

Level

Fixed

X

All including Self

Invalid

5

X

Lowest Priority, NMI, INIT, SMI, Start-Up

X

All excluding Self

Valid

Edge

All Modes

1

X

All excluding Self

Valid

2

Level

Fixed, Lowest Priority

1

, NMI

X

All excluding Self

Invalid

5

Level

SMI, Start-Up

X

All excluding Self

Valid

3

Level

INIT

X

X

Invalid

5

Level

SMI, Start-Up

X

NOTES:

1. The ability of a processor to send a lowest priority IPI is model specific.
2. Treated as edge triggered if level bit is set to 1, otherwise ignored.
3. Treated as edge triggered when Level bit is set to 1; treated as “INIT Level Deassert” message when level bit is set to 0 (deassert). 

Only INIT level deassert messages are allowed to have the level bit set to 0. For all other messages the level bit must be set to 1.

4. X means the setting is ignored.
5. The behavior of the APIC is undefined.

Table 10-4 Valid Combinations for the P6 Family Processors’

Local APIC Interrupt Command Register (Contd.)

Destination 

Shorthand

Valid/

Invalid

Trigger Mode

Delivery Mode

Destination Mode