18-120 Vol. 3B

PERFORMANCE MONITORING

overflow or incremented condition. The external signalling of the event on the pins will lag the internal event by 
a few clocks as the signals are latched and buffered.

While a counter need not be stopped to sample its contents, it must be stopped and cleared or preset before 
switching to a new event. It is not possible to set one counter separately. If only one event needs to be changed, 
the CESR register must be read, the appropriate bits modified, and all bits must then be written back to CESR. At 
reset, all bits in the CESR register are cleared.

18.23.2  Use of the Performance-Monitoring Pins

When performance-monitor pins PM0/BP0 and/or PM1/BP1 are configured to indicate when the performance-
monitor counter has incremented and an “occurrence event” is being counted, the associated pin is asserted (high) 
each time the event occurs. When a “duration event” is being counted, the associated PM pin is asserted for the 
entire duration of the event. When the performance-monitor pins are configured to indicate when the counter has 
overflowed, the associated PM pin is asserted when the counter has overflowed.
When the PM0/BP0 and/or PM1/BP1 pins are configured to signal that a counter has incremented, it should be 
noted that although the counters may increment by 1 or 2 in a single clock, the pins can only indicate that the event 
occurred. Moreover, since the internal clock frequency may be higher than the external clock frequency, a single 
external clock may correspond to multiple internal clocks.
A “count up to” function may be provided when the event pin is programmed to signal an overflow of the counter. 
Because the counters are 40 bits, a carry out of bit 39 indicates an overflow. A counter may be preset to a specific 
value less then 2

40

 − 1. After the counter has been enabled and the prescribed number of events has transpired, 

the counter will overflow. 
Approximately 5 clocks later, the overflow is indicated externally and appropriate action, such as signaling an inter-
rupt, may then be taken.
The PM0/BP0 and PM1/BP1 pins also serve to indicate breakpoint matches during in-circuit emulation, during which 
time the counter increment or overflow function of these pins is not available. After RESET, the PM0/BP0 and 
PM1/BP1 pins are configured for performance monitoring, however a hardware debugger may reconfigure these 
pins to indicate breakpoint matches.

18.23.3 Events 

Counted

Events that performance-monitoring counters can be set to count and record (using CTR0 and CTR1) are divided in 
two categories: occurrence and duration:

•

Occurrence events — Counts are incremented each time an event takes place. If PM0/BP0 or PM1/BP1 pins 
are used to indicate when a counter increments, the pins are asserted each clock counters increment. But if an 
event happens twice in one clock, the counter increments by 2 (the pins are asserted only once).

•

Duration events — Counters increment the total number of clocks that the condition is true. When used to 
indicate when counters increment, PM0/BP0 and/or PM1/BP1 pins are asserted for the duration.