4-40 Vol. 3A

PAGING

A processor may or may not implement any of the paging-structure caches. Software should rely on neither their 
presence nor their absence. The processor may invalidate entries in these caches at any time. Because the 
processor may create the cache entries at the time of translation and not update them following subsequent modi-
fications to the paging structures in memory, software should take care to invalidate the cache entries appropri-
ately when causing such modifications. The invalidation of TLBs and the paging-structure caches is described in 
Section 4.10.4.

4.10.3.2   Using the Paging-Structure Caches to Translate Linear Addresses

When a linear address is accessed, the processor uses a procedure such as the following to determine the physical 
address to which it translates and whether the access should be allowed:

•

If the processor finds a TLB entry that is for the page number of the linear address and that is associated with 
the current PCID (or which is global), it may use the physical address, access rights, and other attributes from 
that entry.

•

If the processor does not find a relevant TLB entry, it may use the upper bits of the linear address to select an 
entry from the PDE cache that is associated with the current PCID (Section 4.10.3.1 indicates which bits are 
used in each paging mode). It can then use that entry to complete the translation process (locating a PTE, etc.) 
as if it had traversed the PDE (and, for IA-32e paging, the PDPTE and PML4E) corresponding to the PDE-cache 
entry.

•

The following items apply when IA-32e paging is used:
— If the processor does not find a relevant TLB entry or a relevant PDE-cache entry, it may use bits 47:30 of 

the linear address to select an entry from the PDPTE cache that is associated with the current PCID. It can 
then use that entry to complete the translation process (locating a PDE, etc.) as if it had traversed the 
PDPTE and the PML4E corresponding to the PDPTE-cache entry.

— If the processor does not find a relevant TLB entry, a relevant PDE-cache entry, or a relevant PDPTE-cache 

entry, it may use bits 47:39 of the linear address to select an entry from the PML4 cache that is associated 
with the current PCID. It can then use that entry to complete the translation process (locating a PDPTE, 
etc.) as if it had traversed the corresponding PML4E.

(Any of the above steps would be skipped if the processor does not support the cache in question.)
If the processor does not find a TLB or paging-structure-cache entry for the linear address, it uses the linear 
address to traverse the entire paging-structure hierarchy, as described in Section 4.3, Section 4.4.2, and Section 
4.5.

4.10.3.3   Multiple Cached Entries for a Single Paging-Structure Entry

The paging-structure caches and TLBs may contain multiple entries associated with a single PCID and with infor-
mation derived from a single paging-structure entry. The following items give some examples for IA-32e paging:

•

Suppose that two PML4Es contain the same physical address and thus reference the same page-directory-
pointer table. Any PDPTE in that table may result in two PDPTE-cache entries, each associated with a different 
set of linear addresses. Specifically, suppose that the n

1

th

 and n

2

th

 entries in the PML4 table contain the same 

physical address. This implies that the physical address in the m

th

 PDPTE in the page-directory-pointer table 

would appear in the PDPTE-cache entries associated with both p

1

 and p

2

, where (p

1

» 9) = n

1

, (p

2

» 9) = n

2

, 

and (p

1

& 1FFH) = (p

2

& 1FFH) = m. This is because both PDPTE-cache entries use the same PDPTE, one 

resulting from a reference from the n

1

th

 PML4E and one from the n

2

th

 PML4E.

•

Suppose that the first PML4E (i.e., the one in position 0) contains the physical address X in CR3 (the physical 
address of the PML4 table). This implies the following:
— Any PML4-cache entry associated with linear addresses with 0 in bits 47:39 contains address X.
— Any PDPTE-cache entry associated with linear addresses with 0 in bits 47:30 contains address X. This is 

because the translation for a linear address for which the value of bits 47:30 is 0 uses the value of 
bits 47:39 (0) to locate a page-directory-pointer table at address X (the address of the PML4 table). It then 
uses the value of bits 38:30 (also 0) to find address X again and to store that address in the PDPTE-cache 
entry.