Vol. 3A 13-1

CHAPTER 13

SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND

PROCESSOR EXTENDED STATES

This chapter describes system programming features for instruction set extensions operating on the processor 
state extension known as the SSE state (XMM registers, MXCSR) and for other processor extended states. Instruc-
tion set extensions operating on the SSE state include the streaming SIMD extensions (SSE), streaming SIMD 
extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), Supplemental SSE3 (SSSE3), and SSE4. Collectively, 
these are called  SSE extensions

1

 and the corresponding instructions SSE instructions. FXSAVE/FXRSTOR 

instructions can be used save/restore SSE state along with FP state. See Section 10.5 in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 1 for information about FXSAVE and FXRSTOR.
Sections 13.1 through 13.4 cover system programming requirements to enable the SSE extensions, providing 
operating system or executive support for the SSE extensions, SIMD floating-point exceptions, exception handling, 
and task (context) switching. These sections primarily discuss use of FXSAVE/FXRSTOR to save/restore SSE state.
XSAVE feature set refers to extensions to the Intel architecture that will allow system executives to implement 
support for multiple processor extended states along with FP/SSE states that may be introduced over time without 
requiring the system executive to be modified each time a new processor state extension is introduced. XSAVE 
feature set provide mechanisms to enumerate the supported extended states, enable some or all of them for soft-
ware use, instructions to save/restore the states and enumerate the layout of the states when saved to memory. 
XSAVE/XRSTOR instructions are part of the XSAVE feature set. These instructions are introduced after the intro-
duction of FP/SSE states but can be used to manage legacy FP/SSE state along with processor extended states. See 
CHAPTER 13 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for information 
about XSAVE feature set.
System programming for managing processor extended states is described in sections 13.5 through 13.6. XSAVE 
feature set is designed to be compatible with FXSAVE/FXRSTOR and hence much of the material through sections 
13.1 to 13.4 related to SSE state also applies to XSAVE feature set with the exception of enumeration and 
saving/restoring state.
XSAVE Compaction is an XSAVE feature that allows operating systems to allocate space for only the states saved 
to conserve memory usage. A new instruction called XSAVEC is introduced to save extended states in compacted 
format and XRSTOR instruction is enhanced to comprehend compacted format. System programming for managing 
processor extended states in compacted format is also described in section 13.5.
Supervisor state is an extended state that can only be accessed in ring 0. XSAVE feature set has been enhanced 
to manage supervisor states. Two new ring 0 instructions, XSAVES/XRSTORS, are introduced to save/restore 
supervisor states along with other XSAVE managed states. They are privileged instruction and only operate in 
compacted format. System programming for managing supervisor states in described in section 13.7.
Each XSAVE managed features may have additional feature specific system programming requirements such as 
exception handlers etc. Feature specific system programming requirements for XSAVE managed features are 
described in section 13.8.

13.1 

PROVIDING OPERATING SYSTEM SUPPORT FOR SSE EXTENSIONS

To use SSE extensions, the operating system or executive must provide support for initializing the processor to use 
these extensions, for handling SIMD floating-point exceptions, and for using FXSAVE and FXRSTOR (Section 10.5 
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1) to manage context. XSAVE 
feature set can also be used to manage SSE state along with other processor extended states as described in 13.5. 
This section primarily focuses on using FXSAVE/FXRSTOR to manage SSE state. Because SSE extensions share the 
same state, experience the same sets of non-numerical and numerical exception behavior, these guidelines that 
apply to SSE also apply to other sets of SIMD extensions that operate on the same processor state and subject to 
the same sets of non-numerical and numerical exception behavior. 

1. The collection also includes PCLMULQDQ and AES instructions operating on XMM state.