Vol. 3A 10-43
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
Virtualization Technology for Directed I/O, Revision 1.3 for the routing of interrupts from MSI-capable devices to
local APIC units operating in x2APIC mode.
10.12.7 Initialization by System Software
Routing of device interrupts to local APIC units operating in x2APIC mode requires use of the interrupt-remapping
architecture specified in the Intel
®
Virtualization Technology for Directed I/O, Revision 1.3. Because of this, BIOS
must enumerate support for and software must enable this interrupt remapping with Extended Interrupt Mode
Enabled before it enabling x2APIC mode in the local APIC units.
The ACPI interfaces for the x2APIC are described in Section 5.2, “ACPI System Description Tables,” of the Advanced
Configuration and Power Interface Specification, Revision 4.0a (http://www.acpi.info/spec.htm). The default
behavior for BIOS is to pass the control to the operating system with the local x2APICs in xAPIC mode if all APIC
IDs reported by CPUID.0BH:EDX are less than 255, and in x2APIC mode if there are any logical processor reporting
an APIC ID of 255 or greater.
10.12.8 CPUID Extensions And Topology Enumeration
For Intel 64 and IA-32 processors that support x2APIC, a value of 1 reported by CPUID.01H:ECX[21] indicates that
the processor supports x2APIC and the extended topology enumeration leaf (CPUID.0BH).
The extended topology enumeration leaf can be accessed by executing CPUID with EAX = 0BH. Processors that do
not support x2APIC may support CPUID leaf 0BH. Software can detect the availability of the extended topology
enumeration leaf (0BH) by performing two steps:
•
Check maximum input value for basic CPUID information by executing CPUID with EAX= 0. If CPUID.0H:EAX is
greater than or equal or 11 (0BH), then proceed to next step
•
Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero.
If both of the above conditions are true, extended topology enumeration leaf is available. If available, the extended
topology enumeration leaf is the preferred mechanism for enumerating topology. The presence of CPUID leaf 0BH
in a processor does not guarantee support for x2APIC. If CPUID.EAX=0BH, ECX=0H:EBX returns zero and
maximum input value for basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not supported on
that processor.
The extended topology enumeration leaf is intended to assist software with enumerating processor topology on
systems that requires 32-bit x2APIC IDs to address individual logical processors. Details of CPUID leaf 0BH can be
found in the reference pages of CPUID in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.
Processor topology enumeration algorithm for processors supporting the extended topology enumeration leaf of
CPUID and processors that do not support CPUID leaf 0BH are treated in Section 8.9.4, “Algorithm for Three-Level
Mappings of APIC_ID”.
10.12.8.1 Consistency of APIC IDs and CPUID
The consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32-bit value returned in
CPUID.0BH:EDX is facilitated by processor hardware.
CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows BIOS to determine if a system
has processors with IDs exceeding the 8-bit initial APIC ID limit (CPUID.01H:EBX[31:24]). Initial APIC ID
(CPUID.01H:EBX[31:24]) is always equal to CPUID.0BH:EDX[7:0].
If the values of CPUID.0BH:EDX reported by all logical processors in a system are less than 255, BIOS can transfer
control to OS in xAPIC mode.
If the values of CPUID.0BH:EDX reported by some logical processors in a system are greater or equal than 255,
BIOS must support two options to hand off to OS:
•
If BIOS enables logical processors with x2APIC IDs greater than 255, then it should enable X2APIC in Boot
Strap Processor (BSP) and all Application Processors (AP) before passing control to the OS. Application
requiring processor topology information must use OS provided services based on x2APIC IDs or CPUID.0BH
leaf.