Vol. 3B 14-5

POWER AND THERMAL MANAGEMENT

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When the user has indicated a policy preference of power savings over performance, OS power management 
may want to disable IDA while that policy is in effect.

14.3.3 

Intel Turbo Boost Technology

Intel Turbo Boost Technology is supported in Intel Core i7 processors and Intel Xeon processors based on Intel

®

 

microarchitecture code name Nehalem. It uses the same principle of leveraging thermal headroom to dynamically 
increase processor performance for single-threaded and multi-threaded/multi-tasking environment. The program-
ming interface described in Section 14.3.2 also applies to Intel Turbo Boost Technology.

14.3.4 

Performance and Energy Bias Hint support

Intel 64 processors may support additional software hint to guide the hardware heuristic of power management 
features to favor increasing dynamic performance or conserve energy consumption. 
Software can detect the processor's capability to support the performance-energy bias preference hint by exam-
ining bit 3 of ECX in CPUID leaf 6. The processor supports this capability if CPUID.06H:ECX.SETBH[bit 3] is set and 
it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Software can program the lowest four bits of IA32_ENERGY_PERF_BIAS MSR with a value from 0 - 15. The values 
represent a sliding scale, where a value of 0 (the default reset value) corresponds to a hint preference for highest 
performance and a value of 15 corresponds to the maximum energy savings. A value of 7 roughly translates into a 
hint to balance performance with energy consumption.

The layout of IA32_ENERGY_PERF_BIAS is shown in Figure 14-3. The scope of IA32_ENERGY_PERF_BIAS is per 
logical processor, which means that each of the logical processors in the package can be programmed with a 
different value. This may be especially important in virtualization scenarios, where the performance / energy 
requirements of one logical processor may differ from the other. Conflicting “hints” from various logical processors 
at higher hierarchy level will be resolved in favor of performance over energy savings. 
Software can use whatever criteria it sees fit to program the MSR with an appropriate value. However, the value 
only serves as a hint to the hardware and the actual impact on performance and energy savings is model specific.

14.4 

HARDWARE-CONTROLLED PERFORMANCE STATES (HWP)

Intel processors may contain support for Hardware-Controlled Performance States (HWP), which autonomously 
selects performance states while utilizing OS supplied performance guidance hints. The Enhanced Intel Speed-
Step

®

 Technology provides a means for the OS to control and monitor discrete frequency-based operating points 

via the IA32_PERF_CTL and IA32_PERF_STATUS MSRs. 
In contrast, HWP is an implementation of the ACPI-defined Collaborative Processor Performance Control (CPPC), 
which specifies that the platform enumerate a continuous, abstract unit-less, performance value scale that is not 
tied to a specific performance state / frequency by definition. While the enumerated scale is roughly linear in terms 
of a delivered integer workload performance result, the OS is required to characterize the performance value range 
to comprehend the delivered performance for an applied workload. 

Figure 14-3.  IA32_ENERGY_PERF_BIAS Register

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0

Reserved

Energy Policy Preference Hint

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