Vol. 3A 4-33

PAGING

Bits reserved in the paging-structure entries are reserved for future functionality. Software developers should 
be aware that such bits may be used in the future and that a paging-structure entry that causes a page-fault 
exception on one processor might not do so in the future.

•

I/D flag (bit 4).
This flag is 1 if (1) the access causing the page-fault exception was an instruction fetch; and (2) either 
(a) CR4.SMEP = 1; or (b) both (i) CR4.PAE = 1 (either PAE paging or IA-32e paging is in use); and 
(ii) IA32_EFER.NXE = 1. Otherwise, the flag is 0. This flag describes the access causing the page-fault 
exception, not the access rights specified by paging.

•

PK flag (bit 5).
This flag is 1 if (1) IA32_EFER.LMA = CR4.PKE = 1; (2) the access causing the page-fault exception was a data 
access; (3) the linear address was a user-mode address with protection key i; and (5) the PKRU register (see 
Section 4.6.2) is such that either (a) ADi = 1; or (b) the following all hold: (i) WDi = 1; (ii) the access is a write 
access; and (iii) either CR0.WP = 1 or the access causing the page-fault exception was a user-mode access.

•

SGX flag (bit 15).
This flag is 1 if the exception is unrelated to paging and resulted from violation of SGX-specific access-control 
requirements. Because such a violation can occur only if there is no ordinary page fault, this flag is set only if 
the P flag (bit 0) is 1 and the RSVD flag (bit 3) and the PK flag (bit 5) are both 0.

Page-fault exceptions occur only due to an attempt to use a linear address. Failures to load the PDPTE registers 
with PAE paging (see Section 4.4.1) cause general-protection exceptions (#GP(0)) and not page-fault exceptions.

4.8 

ACCESSED AND DIRTY FLAGS

For any paging-structure entry that is used during linear-address translation, bit 5 is the accessed flag.

1

 For 

paging-structure entries that map a page (as opposed to referencing another paging structure), bit 6 is the dirty 
flag. These flags are provided for use by memory-management software to manage the transfer of pages and 
paging structures into and out of physical memory.
Whenever the processor uses a paging-structure entry as part of linear-address translation, it sets the accessed 
flag in that entry (if it is not already set).
Whenever there is a write to a linear address, the processor sets the dirty flag (if it is not already set) in the paging-
structure entry that identifies the final physical address for the linear address (either a PTE or a paging-structure 
entry in which the PS flag is 1).
Memory-management software may clear these flags when a page or a paging structure is initially loaded into 
physical memory. These flags are “sticky,” meaning that, once set, the processor does not clear them; only soft-
ware can clear them.
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see 

Section 4.10). This fact implies that, if software changes an accessed flag or a dirty flag from 1 to 0, the processor 

might not set the corresponding bit in memory on a subsequent access using an affected linear address (see 
Section 4.10.4.3). See Section 4.10.4.2 for how software can ensure that these bits are updated as desired.

NOTE

The accesses used by the processor to set these flags may or may not be exposed to the 
processor’s self-modifying code detection logic. If the processor is executing code from the same 
memory area that is being used for the paging structures, the setting of these flags may or may not 
result in an immediate change to the executing code stream.

1. Some past processors had errata for some page faults that occur when there is no translation for the linear address because the P 

flag was 0 in one of the paging-structure entries used to translate that address. Due to these errata, some such page faults pro-

duced error codes that cleared bit 0 (P flag) and set bit 3 (RSVD flag).

1. With PAE paging, the PDPTEs are not used during linear-address translation but only to load the PDPTE registers for some execu-

tions of the MOV CR instruction (see Section 4.4.1). For this reason, the PDPTEs do not contain accessed flags with PAE paging.