Vol. 3B 18-113

PERFORMANCE MONITORING

— 11B: Match transaction from more than one dual-core modules in the physical package

•

Fill_Eviction (bits 57:56): The valid encodings are
— 00B: Match any transactions 
— 01B: Match transactions that fill L3
— 10B: Match transactions that fill L3 without an eviction
— 11B: Match transaction fill L3 with an eviction

•

Cross_Snoop (bit 58): The encodings are

\

— 0B: Match any transactions 
— 1B: Match cross snoop transactions

For each counting clock domain, if all eight attributes match, event logic signals to increment the event count field.

18.21.3  GSNPQ Event Interface

The layout of MSR_EMON_L3_CTR_CTL2 and MSR_EMON_L3_CTR_CTL3 is given in Figure 18-58. Counting starts 
after software writes a non-zero value to one or more of the upper 32 bits. 
The event mask field (bits 58:32) consists of the following six attributes:

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Agent_Select (bits 37:32): The definition of this field differs slightly between Intel Xeon processor 7100 and 
7400. 

•

For Intel Xeon processor 7100 series, each of the lowest 4 bits specifies a logical processor in the physical 
package. The lowest two bits corresponds to two logical processors in the first processor core, the next two bits 
corresponds to two logical processors in the second processor core. Bit 36 specifies other symmetric agent 
transactions. Bit 37 specifies central agent transactions. 3FH encoding matches transactions from any logical 
processor.
For Intel Xeon processor 7400 series, each of the lowest 3 bits specifies a dual-core module in the physical 
package. Bit 37 specifies central agent transactions. 

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Type_Match (bits 43:38): Specifies transaction types. If all six bits are set, event count will include any 
transaction types.

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Snoop_Match: (bits 46:44): The three bits specify (in ascending bit position) clean snoop result, HIT snoop 
result, and HITM snoop results respectively.

•

L2_State (bits 53:47): Each bit specifies an L3 coherency state. 

•

Core_Module_Select (bits 56:54): Bit 56 enables Core_Module_Select matching. If bit 56 is clear, 
Core_Module_Select encoding is ignored. The valid encodings for the lower two bits (bit 55, 54) differ slightly 
between Intel Xeon processor 7100 and 7400.
For Intel Xeon processor 7100 series, if bit 56 is set, the valid encodings for the lower two bits (bit 55, 54) are
— 00B: Match transactions from only one core (irrespective which core) in the physical package
— 01B: Match transactions from this core and not the other core
— 10B: Match transactions from the other core in the physical package, but not this core
— 11B: Match transaction from both cores in the physical package
For Intel Xeon processor 7400 series, if bit 56 is set, the valid encodings for the lower two bits (bit 55, 54) are
— 00B: Match transactions from only one dual-core module (irrespective which module) in the physical 

package.

— 01B: Match transactions from one or more dual-core modules.
— 10B: Match transactions from two or more dual-core modules.
— 11B: Match transaction from all three dual-core modules in the physical package.

•

Block_Snoop (bit 57): specifies blocked snoop.

For each counting clock domain, if all six attributes match, event logic signals to increment the event count field.