13-10 Vol. 3A
SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES
For instance, the OS can supply instructions in the XSAVE feature set with a bit vector in EDX:EAX with the two
least significant bits (corresponding to x87 FPU and SSE state) equal to 0. Then, the XSAVE instruction will not
write the processor’s x87 FPU and SSE state into memory. Similarly, the XRSTOR instruction executed with a value
in EDX:EAX with the least two significant bit equal to 0 will not restore nor initialize the processor’s x87 FPU and
SSE state.
The processor’s action as a result of executing XRSTOR is given in Section 13.8 of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 1. The instruction may be used to initialize x87 FPU or XMM regis-
ters. When the MXCSR register is updated from memory, reserved bit checking is enforced. The saving/restoring of
MXCSR is bound to the SSE state, independent of the x87 FPU state. The action of XSAVE is given in Section 13.7
of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
13.7
THE XSAVE FEATURE SET AND PROCESSOR SUPERVISOR STATE
MANAGEMENT
Supervisor state is a processor state that is only accessible in ring 0. An extension to XSAVE feature set, enumer-
ated by CPUID.(EAX=0DH, ECX=1).EAX[bit 3] allows the management of the supervisor states using XSAVE
feature set. See Chapter 13 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for the
details of the supervisor state XSAVE feature set extension. The supervisor state extension includes the following:
•
CPUID enhancements to enumerate the set of supervisor states and their sizes that can be managed by XSAVE
feature set.
•
A new MSR IA32_XSS to enable XSAVE feature set to manage one or more enumerated supervisor states.
•
A new pair of privileged save/restore instructions, XSAVES and XRSTORS, to save/restore supervisor states
along with other XSAVE managed feature states.
The guidelines to enable XSAVE feature set to manage supervisor state are very similar to the steps outlines in
Section 13.6 with the differences outline below. The set of supervisor states that can be managed by XSAVE feature
set is enumerated in (EAX=0DH, ECX=1).EDX:ECX. XSAVE managed supervisor states are enabled in IA32_XSS
MSR instead of XCR0 control register. There are semantic differences between user states enabled in XCR0 and
supervisor state enabled in IA32_XSS MSR. A supervisor state enabled in IA32_XSS MSR:
•
May be accessed via other mechanisms such as RDMSR/WRMSR even when they are not enabled in IA32_XSS
MSR. Enabling a supervisor state in the IA32_XSS MSR merely indicates that the state can be saved/restored
using XSAVES/XRSTORS instructions.
•
May have side effects when saving/restoring the state such as disabling/enabling feature associated with the
state. This behavior is feature specific and will be documented along with the feature description.
•
May generate faults when saving/restoring the state. XSAVES/XRSTORS will follow the faulting behavior of
RDMSR/WRMSR respectively if the corresponding state is also accessible using RDMSR/WRMSR.
•
XRSTORS may fault when restoring the state for supervisor features that are already enabled via feature
specific mechanisms. This behavior is feature specific and will be documented along with the feature
description.
When a supervisor state is disabled via a feature specific mechanism, the state does not automatically get marked
as INIT. Hence XSAVES/XRSTORS will continue to save/restore the state subject to available optimizations. If the
software does not intend to preserve the state when it disables the feature, it should initialize it to hardware INIT
value with XRSTORS instruction so that XSAVES/XRSTORS perform optimally for that state.
13.8
SYSTEM PROGRAMMING FOR XSAVE MANAGED FEATURES
This section describes system programming requirement for each XSAVE managed features that are feature
specific such as exception handling.