6-16 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

The segment selector index field provides an index into the IDT, GDT, or current LDT to the segment or gate 
selector being referenced by the error code. In some cases the error code is null (all bits are clear except possibly 
EXT). A null error code indicates that the error was not caused by a reference to a specific segment or that a null 
segment selector was referenced in an operation.
The format of the error code is different for page-fault exceptions (#PF). See the “Interrupt 14—Page-Fault Excep-
tion (#PF)” section in this chapter.
The error code is pushed on the stack as a doubleword or word (depending on the default interrupt, trap, or task 
gate size). To keep the stack aligned for doubleword pushes, the upper half of the error code is reserved. Note that 
the error code is not popped when the IRET instruction is executed to return from an exception handler, so the 
handler must remove the error code before executing a return.
Error codes are not pushed on the stack for exceptions that are generated externally (with the INTR or LINT[1:0] 
pins) or the INT n instruction, even if an error code is normally produced for those exceptions.

6.14 

EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE

In 64-bit mode, interrupt and exception handling is similar to what has been described for non-64-bit modes. The 
following are the exceptions:

•

All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply to the SMI handler).

•

The size of interrupt-stack pushes is fixed at 64 bits; and the processor uses 8-byte, zero extended stores.

•

The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy modes, this push is conditional 
and based on a change in current privilege level (CPL).

•

The new SS is set to NULL if there is a change in CPL.

•

IRET behavior changes.

•

There is a new interrupt stack-switch mechanism.

•

The alignment of interrupt stack frame is different.

6.14.1 

64-Bit Mode IDT

Interrupt and trap gates are 16 bytes in length to provide a 64-bit offset for the instruction pointer (RIP). The 64-
bit RIP referenced by interrupt-gate descriptors allows an interrupt service routine to be located anywhere in the 
linear-address space. See Figure 6-7.

Figure 6-6.  Error Code

31

0

Reserved

I

D
T

T

I

1

2

3

Segment Selector Index

E
X
T