Vol. 3A 10-31

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

Bit 12 of the Spurious Interrupt Vector Register is reserved to 0 if the processor does not support suppression of 
EOI broadcasts. Support for EOI-broadcast suppression is reported in bit 24 in the Local APIC Version Register (see 
Section 10.4.8); the feature is supported if that bit is set to 1. When supported, the feature is available in both 
xAPIC mode and x2APIC mode.
System software desiring to perform directed EOIs for level-triggered interrupts should set bit 12 of the Spurious 
Interrupt Vector Register and follow each the EOI to the local xAPIC for a level triggered interrupt with a directed 
EOI to the I/O APIC generating the interrupt (this is done by writing to the I/O APIC’s EOI register). System soft-
ware performing directed EOIs must retain a mapping associating level-triggered interrupts with the I/O APICs in 
the system.

10.8.6 

Task Priority in IA-32e Mode

In IA-32e mode, operating systems can manage the 16 interrupt-priority classes (see Section 10.8.3, “Interrupt, 
Task, and Processor Priority”) explicitly using the task priority register (TPR). Operating systems can use the TPR 
to temporarily block specific (low-priority) interrupts from interrupting a high-priority task. This is done by loading 
TPR with a value in which the task-priority class corresponds to the highest interrupt-priority class that is to be 
blocked. For example: 

•

Loading the TPR with a task-priority class of 8 (01000B) blocks all interrupts with an interrupt-priority class of 
8 or less while allowing all interrupts with an interrupt-priority class of 9 or more to be recognized.

•

Loading the TPR with a task-priority class of 0 enables all external interrupts. 

•

Loading the TPR with a task-priority class of 0FH (01111B) disables all external interrupts. 

The TPR (shown in Figure 10-18) is cleared to 0 on reset. In 64-bit mode, software can read and write the TPR 
using an alternate interface, MOV CR8 instruction. The new task-priority class is established when the MOV CR8 
instruction completes execution. Software does not need to force serialization after loading the TPR using MOV 
CR8. 
Use of the MOV CRn instruction requires a privilege level of 0. Programs running at privilege level greater than 0 
cannot read or write the TPR. An attempt to do so causes a general-protection exception. The TPR is abstracted 
from the interrupt controller (IC), which prioritizes and manages external interrupt delivery to the processor. The 
IC can be an external device, such as an APIC or 8259. Typically, the IC provides a priority mechanism similar or 
identical to the TPR. The IC, however, is considered implementation-dependent with the under-lying priority mech-
anisms subject to change. CR8, by contrast, is part of the Intel 64 architecture. Software can depend on this defi-
nition remaining unchanged. 
Figure 10-22 shows the layout of CR8; only the low four bits are used. The remaining 60 bits are reserved and 
must be written with zeros. Failure to do this causes a general-protection exception.

10.8.6.1   Interaction of Task Priorities between CR8 and APIC

The first implementation of Intel 64 architecture includes a local advanced programmable interrupt controller 
(APIC) that is similar to the APIC used with previous IA-32 processors. Some aspects of the local APIC affect the 
operation of the architecturally defined task priority register and the programming interface using CR8.
Notable CR8 and APIC interactions are:

•

The processor powers up with the local APIC enabled.

•

The APIC must be enabled for CR8 to function as the TPR. Writes to CR8 are reflected into the APIC Task Priority 
Register.

Figure 10-22.  CR8 Register

63

0

Value after reset: 0H

3

4

Reserved