Vol. 3A 2-25

SYSTEM ARCHITECTURE OVERVIEW

Details of programmable and fixed-function performance monitoring counters for each processor generation are 
described in Chapter 18, “Performance Monitoring”.
The programmable performance counters can support counting either the occurrence or duration of events. Events 
that can be monitored on programmable counters generally are model specific (except for architectural perfor-
mance events enumerated by CPUID leaf 0AH); they may include the number of instructions decoded, interrupts 
received, or the number of cache loads. Individual counters can be set up to monitor different events. Use the 
system instruction WRMSR to set up values in one of the IA32_PERFEVTSELx MSR, in one of the 45 ESCRs and one 
of the 18 CCCR MSRs (for Pentium 4 and Intel Xeon processors); or in the PerfEvtSel0 or the PerfEvtSel1 MSR (for 
the P6 family processors). The RDPMC instruction loads the current count from the selected counter into the 
EDX:EAX registers.
Fixed-function performance counters record only specific events that are defined in Chapter 19, “Performance 
Monitoring Events”, and the width/number of fixed-function counters are enumerated by CPUID leaf 0AH.
The time-stamp counter is a model-specific 64-bit counter that is reset to zero each time the processor is reset. If 
not reset, the counter will increment ~9.5 x 10

16 

times per year when the processor is operating at a clock rate 

of 3GHz. At this clock frequency, it would take over 190 years for the counter to wrap around. The RDTSC 
instruction loads the current count of the time-stamp counter into the EDX:EAX registers.
See Section 18.1, “Performance Monitoring Overview,” and Section 17.15, “Time-Stamp Counter,” for more infor-
mation about the performance monitoring and time-stamp counters.
The RDTSC instruction was introduced into the IA-32 architecture with the Pentium processor. The RDPMC instruc-
tion was introduced into the IA-32 architecture with the Pentium Pro processor and the Pentium processor with 
MMX technology. Earlier Pentium processors have two performance-monitoring counters, but they can be read only 
with the RDMSR instruction, and only at privilege level 0.

2.8.6.1  

Reading Counters in 64-Bit Mode

In 64-bit mode, RDTSC operates the same as in protected mode. The count in the time-stamp counter is stored in 
EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).
RDPMC requires an index to specify the offset of the performance-monitoring counter. In 64-bit mode for Pentium 
4 or Intel Xeon processor families, the index is specified in ECX[30:0]. The current count of the performance-moni-
toring counter is stored in EDX:EAX (or RDX[31:0]:RAX[31:0] with RDX[63:32]:RAX[63:32] cleared).

2.8.7 

Reading and Writing Model-Specific Registers

The RDMSR (read model-specific register) and WRMSR (write model-specific register) instructions allow a 
processor’s 64-bit model-specific registers (MSRs) to be read and written, respectively. The MSR to be read or 
written is specified by the value in the ECX register.

RDMSR reads the value from the specified MSR to the EDX:EAX registers; WRMSR writes the value in the EDX:EAX 
registers to the specified MSR. RDMSR and WRMSR were introduced into the IA-32 architecture with the Pentium 
processor.
See Section 9.4, “Model-Specific Registers (MSRs),” for more information.

2.8.7.1  

Reading and Writing Model-Specific Registers in 64-Bit Mode

RDMSR and WRMSR require an index to specify the address of an MSR. In 64-bit mode, the index is 32 bits; it is 
specified using ECX.

2.8.8 

Enabling Processor Extended States

The XSETBV instruction is required to enable OS support of individual processor extended states in XCR0 (see 
Section 2.6).