3-6 Vol. 3A

PROTECTED-MODE MEMORY MANAGEMENT

protection facilities. For example, it lets read-write protection be enforced on a page-by-page basis. The paging 
mechanism also provides two-level user-supervisor protection that can also be specified on a page-by-page basis.

3.3 PHYSICAL 

ADDRESS 

SPACE

In protected mode, the IA-32 architecture provides a normal physical address space of 4 GBytes (2

32

 

bytes). This 

is the address space that the processor can address on its address bus. This address space is flat (unsegmented), 
with addresses ranging continuously from 0 to FFFFFFFFH. This physical address space can be mapped to read-
write memory, read-only memory, and memory mapped I/O. The memory mapping facilities described in this 
chapter can be used to divide this physical memory up into segments and/or pages.
Starting with the Pentium Pro processor, the IA-32 architecture also supports an extension of the physical address 
space to 2

36

 bytes (64 GBytes); with a maximum physical address of FFFFFFFFFH. This extension is invoked in 

either of two ways:

•

Using the physical address extension (PAE) flag, located in bit 5 of control register CR4. 

•

Using the 36-bit page size extension (PSE-36) feature (introduced in the Pentium III processors).

Physical address support has since been extended beyond 36 bits. See Chapter 4, “Paging” for more information 
about 36-bit physical addressing.

3.3.1 Intel

® 

64 Processors and Physical Address Space

On processors that support Intel 64 architecture (CPUID.80000001H:EDX[29] = 1), the size of the physical 
address range is implementation-specific and indicated by CPUID.80000008H:EAX[bits 7-0]. 
For the format of information returned in EAX, see “CPUID—CPU Identification” in Chapter 3 of the Intel® 64 and 
IA-32 Architectures Software Developer’s Manual, Volume 2A. See also: Chapter 4, “Paging.”

3.4 

LOGICAL AND LINEAR ADDRESSES

At the system-architecture level in protected mode, the processor uses two stages of address translation to arrive 
at a physical address: logical-address translation and linear address space paging.
Even with the minimum use of segments, every byte in the processor’s address space is accessed with a logical 
address. A logical address consists of a 16-bit segment selector and a 32-bit offset (see Figure 3-5). The segment 
selector identifies the segment the byte is located in and the offset specifies the location of the byte in the segment 
relative to the base address of the segment. 
The processor translates every logical address into a linear address. A linear address is a 32-bit address in the 
processor’s linear address space. Like the physical address space, the linear address space is a flat (unsegmented), 
2

32

-byte address space, with addresses ranging from 0 to FFFFFFFFH. The linear address space contains all the 

segments and system tables defined for a system. 
To translate a logical address into a linear address, the processor does the following:
1. Uses the offset in the segment selector to locate the segment descriptor for the segment in the GDT or LDT and 

reads it into the processor. (This step is needed only when a new segment selector is loaded into a segment 
register.)

2. Examines the segment descriptor to check the access rights and range of the segment to insure that the 

segment is accessible and that the offset is within the limits of the segment.

3. Adds the base address of the segment from the segment descriptor to the offset to form a linear address.