Vol. 3A 8-29

MULTIPLE-PROCESSOR MANAGEMENT

On Intel Atom family processors that support Intel Hyper-Threading Technology, the MCA facilities are shared 
between all logical processors on the same processor core.

8.7.6 

Debug Registers and Extensions

Each logical processor has its own set of debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and its own debug 
control MSR. These can be set to control and record debug information for each logical processor independently. 
Each logical processor also has its own last branch records (LBR) stack.

8.7.7 

Performance Monitoring Counters

Performance counters and their companion control MSRs are shared between the logical processors within a 
processor core for processors based on Intel NetBurst microarchitecture. As a result, software must manage the 
use of these resources. The performance counter interrupts, events, and precise event monitoring support can be 
set up and allocated on a per thread (per logical processor) basis. 
See Section 18.16, “Performance Monitoring and Intel Hyper-Threading Technology in Processors Based on Intel 
NetBurst

®

 Microarchitecture,” for a discussion of performance monitoring in the Intel Xeon processor MP. 

In Intel Atom processor family that support Intel Hyper-Threading Technology, the performance counters (general-
purpose and fixed-function counters) and their companion control MSRs are duplicated for each logical processor.

8.7.8 IA32_MISC_ENABLE 

MSR

The IA32_MISC_ENABLE MSR (MSR address 1A0H) is generally shared between the logical processors in a 
processor core supporting Intel Hyper-Threading Technology. However, some bit fields within IA32_MISC_ENABLE 
MSR may be duplicated per logical processor. The partition of shared or duplicated bit fields within 
IA32_MISC_ENABLE is implementation dependent. Software should program duplicated fields carefully on all 
logical processors in the system to ensure consistent behavior.

8.7.9 Memory 

Ordering

The logical processors in an Intel 64 or IA-32 processor supporting Intel Hyper-Threading Technology obey the 
same rules for memory ordering as Intel 64 or IA-32 processors without Intel HT Technology (see Section 8.2, 
“Memory Ordering”). Each logical processor uses a processor-ordered memory model that can be further defined 
as “write-ordered with store buffer forwarding.” All mechanisms for strengthening or weakening the memory-
ordering model to handle special programming situations apply to each logical processor.

8.7.10 Serializing 

Instructions

As a general rule, when a logical processor in a processor supporting Intel Hyper-Threading Technology executes a 
serializing instruction, only that logical processor is affected by the operation. An exception to this rule is the 
execution of the WBINVD, INVD, and WRMSR instructions; and the MOV CR instruction when the state of the CD 
flag in control register CR0 is modified. Here, both logical processors are serialized.

8.7.11 Microcode 

Update 

Resources

In an Intel processor supporting Intel Hyper-Threading Technology, the microcode update facilities are shared 
between the logical processors; either logical processor can initiate an update. Each logical processor has its own 
BIOS signature MSR (IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs an update for 
the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logical processors are updated with identical 
information. If logical processors initiate an update simultaneously, the processor core provides the necessary 
synchronization needed to ensure that only one update is performed at a time.