Vol. 3A 11-27

MEMORY CACHE CONTROL

To map the address range from 400000H to 7FFFFFH (4 MBytes to 8 MBytes), a base value of 000400H is entered 
in the PhysBase field and a mask value of FFFC00H is entered in the PhysMask field.

Example 11-2.  Setting-Up Memory for a System

Here is an example of setting up the MTRRs for an system. Assume that the system has the following characteris-
tics:

•

96 MBytes of system memory is mapped as write-back memory (WB) for highest system performance.

•

A custom 4-MByte I/O card is mapped to uncached memory (UC) at a base address of 64 MBytes. This 
restriction forces the 96 MBytes of system memory to be addressed from 0 to 64 MBytes and from 68 MBytes 
to 100 MBytes, leaving a 4-MByte hole for the I/O card. 

•

An 8-MByte graphics card is mapped to write-combining memory (WC) beginning at address A0000000H. 

•

The BIOS area from 15 MBytes to 16 MBytes is mapped to UC memory.

The following settings for the MTRRs will yield the proper mapping of the physical address space for this system 
configuration.

IA32_MTRR_PHYSBASE0 =  0000 0000 0000 0006H
IA32_MTRR_PHYSMASK0 =  0000 000F FC00 0800H  
Caches 0-64 MByte as WB cache type.

IA32_MTRR_PHYSBASE1 =  0000 0000 0400 0006H
IA32_MTRR_PHYSMASK1 =  0000 000F FE00 0800H  
Caches 64-96 MByte as WB cache type.

IA32_MTRR_PHYSBASE2 =  0000 0000 0600 0006H
IA32_MTRR_PHYSMASK2 =  0000 000F FFC0 0800H  
Caches 96-100 MByte as WB cache type.

IA32_MTRR_PHYSBASE3 =  0000 0000 0400 0000H
IA32_MTRR_PHYSMASK3 =  0000 000F FFC0 0800H  
Caches 64-68 MByte as UC cache type.

IA32_MTRR_PHYSBASE4 =  0000 0000 00F0 0000H
IA32_MTRR_PHYSMASK4 =  0000 000F FFF0 0800H  
Caches 15-16 MByte as UC cache type.

IA32_MTRR_PHYSBASE5 =  0000 0000 A000 0001H
IA32_MTRR_PHYSMASK5 =  0000 000F FF80 0800H  
Caches A0000000-A0800000 as WC type.
This MTRR setup uses the ability to overlap any two memory ranges (as long as the ranges are mapped to WB and 
UC memory types) to minimize the number of MTRR registers that are required to configure the memory environ-
ment. This setup also fulfills the requirement that two register pairs are left for operating system usage.

11.11.3.1   Base and Mask Calculations for Greater-Than 36-bit Physical Address Support

For Intel 64 and IA-32 processors that support greater than 36 bits of physical address size, software should query 
CPUID.80000008H to determine the maximum physical address. See the example.

Example 11-3.  Setting-Up Memory for a System with a 40-Bit Address Size

If a processor supports 40-bits of physical address size, then the PhysMask field (in IA32_MTRR_PHYSMASKn 
registers) is 28 bits instead of 24 bits. For this situation, Example 11-2 should be modified as follows:

IA32_MTRR_PHYSBASE0 =  0000 0000 0000 0006H
IA32_MTRR_PHYSMASK0 =  0000 00FF FC00 0800H  
Caches 0-64 MByte as WB cache type.