9-14 Vol. 3A

PROCESSOR MANAGEMENT AND INITIALIZATION

9.9.2 

Switching Back to Real-Address Mode

The processor switches from protected mode back to real-address mode if software clears the PE bit in the CR0 
register with a MOV CR0 instruction. A procedure that re-enters real-address mode should perform the following 
steps:
1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled 

with external circuitry.

2. If paging is enabled, perform the following operations:

— Transfer program control to linear addresses that are identity mapped to physical addresses (that is, linear 

addresses equal physical addresses).

— Insure that the GDT and IDT are in identity mapped pages.
— Clear the PG bit in the CR0 register.
— Move 0H into the CR3 register to flush the TLB.

3. Transfer program control to a readable segment that has a limit of 64 KBytes (FFFFH). This operation loads the 

CS register with the segment limit required in real-address mode.

4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor containing the following values, 

which are appropriate for real-address mode:
— Limit = 64 KBytes (0FFFFH)
— Byte granular (G = 0)
— Expand  up  (E  =  0)
— Writable (W = 1)
— Present  (P  =  1)
— Base = any value
The segment registers must be loaded with non-null segment selectors or the segment registers will be 
unusable in real-address mode. Note that if the segment registers are not reloaded, execution continues using 
the descriptor attributes loaded during protected mode.

5. Execute an LIDT instruction to point to a real-address mode interrupt table that is within the 1-MByte real-

address mode address range.

6. Clear the PE flag in the CR0 register to switch to real-address mode.
7. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction 

queue and loads the appropriate base-address value in the CS register.

8. Load the SS, DS, ES, FS, and GS registers as needed by the real-address mode code. If any of the registers are 

not going to be used in real-address mode, write 0s to them.

9. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware 

operation to enable NMI interrupts.

NOTE

All the code that is executed in steps 1 through 9 must be in a single page and the linear addresses 
in that page must be identity mapped to physical addresses.

9.10 INITIALIZATION 

AND 

MODE SWITCHING EXAMPLE

This section provides an initialization and mode switching example that can be incorporated into an application. 
This code was originally written to initialize the Intel386 processor, but it will execute successfully on the Pentium 
4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The code in this example is intended to reside in EPROM 
and to run following a hardware reset of the processor. The function of the code is to do the following:

•

Establish a basic real-address mode operating environment.