18-116 Vol. 3B

PERFORMANCE MONITORING

NOTE

The performance-monitoring events listed in Chapter 19 are intended to be used as guides for 
performance tuning. Counter values reported are not guaranteed to be accurate and should be 
used as a relative guide for tuning. Known discrepancies are documented where applicable.

The performance-monitoring counters are supported by four MSRs: the performance event select MSRs 
(PerfEvtSel0 and PerfEvtSel1) and the performance counter MSRs (PerfCtr0 and PerfCtr1). These registers can be 
read from and written to using the RDMSR and WRMSR instructions, respectively. They can be accessed using these 
instructions only when operating at privilege level 0. The PerfCtr0 and PerfCtr1 MSRs can be read from any privilege 
level using the RDPMC (read performance-monitoring counters) instruction.

NOTE

The PerfEvtSel0, PerfEvtSel1, PerfCtr0, and PerfCtr1 MSRs and the events listed in Table 19-37 are 
model-specific for P6 family processors. They are not guaranteed to be available in other IA-32 
processors.

18.22.1  PerfEvtSel0 and PerfEvtSel1 MSRs

The PerfEvtSel0 and PerfEvtSel1 MSRs control the operation of the performance-monitoring counters, with one 
register used to set up each counter. They specify the events to be counted, how they should be counted, and the 
privilege levels at which counting should take place. Figure 18-60 shows the flags and fields in these MSRs.
The functions of the flags and fields in the PerfEvtSel0 and PerfEvtSel1 MSRs are as follows:

•

Event select field (bits 0 through 7) — Selects the event logic unit to detect certain microarchitectural 
conditions (see Table 19-37, for a list of events and their 8-bit codes).

•

Unit mask (UMASK) field (bits 8 through 15) — Further qualifies the event logic unit selected in the event 
select field to detect a specific microarchitectural condition. For example, for some cache events, the mask is 
used as a MESI-protocol qualifier of cache states (see Table 19-37).

•

USR (user mode) flag (bit 16) â€” Specifies that events are counted only when the processor is operating at 
privilege levels 1, 2 or 3. This flag can be used in conjunction with the OS flag.

•

OS (operating system mode) flag (bit 17) â€” Specifies that events are counted only when the processor is 
operating at privilege level 0. This flag can be used in conjunction with the USR flag.

•

E (edge detect) flag (bit 18) — Enables (when set) edge detection of events. The processor counts the 
number of deasserted to asserted transitions of any condition that can be expressed by the other fields. The 
mechanism is limited in that it does not permit back-to-back assertions to be distinguished. This mechanism 
allows software to measure not only the fraction of time spent in a particular state, but also the average length 
of time spent in such a state (for example, the time spent waiting for an interrupt to be serviced).

Figure 18-60.  PerfEvtSel0 and PerfEvtSel1 MSRs

31

INV—Invert counter mask
EN—Enable counters

*

INT—APIC interrupt enable
PC—Pin control

8 7

0

Event Select

E—Edge detect
OS—Operating system mode
USR—User Mode

*

Only available in PerfEvtSel0.

Counter Mask 

E

E
N

I

N
T

19

16

18

15

17

20

21

22

23

24

Reserved

I

N
V

P
C

U
S
R

O

S

Unit Mask (UMASK)

(CMASK)