10-8 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.4.3
Enabling or Disabling the Local APIC
The local APIC can be enabled or disabled in either of two ways:
1. Using the APIC global enable/disable flag in the IA32_APIC_BASE MSR (MSR address 1BH; see Figure 10-5):
— When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an IA-32 processor without an
on-chip APIC. The CPUID feature flag for the APIC (see Section 10.4.2, “Presence of the Local APIC”) is also
set to 0.
— When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wire APIC bus cannot be generally
re-enabled until a system hardware reset. The 3-wire bus loses track of arbitration that would be necessary
for complete re-enabling. Certain APIC functionality can be enabled (for example: performance and
thermal monitoring interrupt generation).
— For processors that use Front Side Bus (FSB) delivery of interrupts, software may disable or enable the
APIC by setting and resetting IA32_APIC_BASE[11]. A hardware reset is not required to re-start APIC
functionality, if software guarantees no interrupt will be sent to the APIC as IA32_APIC_BASE[11] is
cleared.
— When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may be lost and the APIC may return
to the state described in Section 10.4.7.1, “Local APIC State After Power-Up or Reset.”
2. Using the APIC software enable/disable flag in the spurious-interrupt vector register (see Figure 10-23):
— If IA32_APIC_BASE[11] is 1, software can temporarily disable a local APIC at any time by clearing the APIC
software enable/disable flag in the spurious-interrupt vector register (see Figure 10-23). The state of the
local APIC when in this software-disabled state is described in Section 10.4.7.2, “Local APIC State After It
Has Been Software Disabled.”
— When the local APIC is in the software-disabled state, it can be re-enabled at any time by setting the APIC
software enable/disable flag to 1.
For the Pentium processor, the APICEN pin (which is shared with the PICD1 pin) is used during power-up or reset
to disable the local APIC.
Note that each entry in the LVT has a mask bit that can be used to inhibit interrupts from being delivered to the
processor from selected local interrupt sources (the LINT0 and LINT1 pins, the APIC timer, the performance-moni-
toring counters, the thermal sensor, and/or the internal APIC error detector).
10.4.4
Local APIC Status and Location
The status and location of the local APIC are contained in the IA32_APIC_BASE MSR (see
). MSR bit
functions are described below:
•
BSP flag, bit 8 ⎯ Indicates if the processor is the bootstrap processor (BSP). See Section 8.4, “Multiple-
Processor (MP) Initialization.” Following a power-up or reset, this flag is set to 1 for the processor selected as
the BSP and set to 0 for the remaining processors (APs).
•
APIC Global Enable flag, bit 11 ⎯ Enables or disables the local APIC (see Section 10.4.3, “Enabling or
Disabling the Local APIC”). This flag is available in the Pentium 4, Intel Xeon, and P6 family processors. It is not
guaranteed to be available or available at the same location in future Intel 64 or IA-32 processors.
•
APIC Base field, bits 12 through 35 ⎯ Specifies the base address of the APIC registers. This 24-bit value is
extended by 12 bits at the low end to form the base address. This automatically aligns the address on a 4-KByte
boundary. Following a power-up or reset, the field is set to FEE0 0000H.
•
Bits 0 through 7, bits 9 and 10, and bits MAXPHYADDR
1
through 63 in the IA32_APIC_BASE MSR are reserved.
1. The MAXPHYADDR is 36 bits for processors that do not support CPUID leaf 80000008H, or indicated by
CPUID.80000008H:EAX[bits 7:0] for processors that support CPUID leaf 80000008H.