18-2 Vol. 3B
PERFORMANCE MONITORING
— Section 18.10, “3rd Generation Intel
Processor Performance Monitoring Facility”
— Section 18.11, “4th Generation Intel
Processor Performance Monitoring Facility”
M Processor Performance Monitoring Facility”
— Section 18.13, “6th Generation Intel
Processor Performance Monitoring Facility”
— Section 18.15, “Performance Monitoring (Processors Based on Intel NetBurst
— Section 18.19, “Performance Monitoring and Dual-Core Technology”
— Section 18.20, “Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache”
— Section 18.22, “Performance Monitoring (P6 Family Processor)”
— Section 18.23, “Performance Monitoring (Pentium Processors)”
18.2 ARCHITECTURAL
PERFORMANCE
MONITORING
Performance monitoring events are architectural when they behave consistently across microarchitectures. Intel
Core Solo and Intel Core Duo processors introduced architectural performance monitoring. The feature provides a
mechanism for software to enumerate performance events and provides configuration and counting facilities for
events.
Architectural performance monitoring does allow for enhancement across processor implementations. The
CPUID.0AH leaf provides version ID for each enhancement. Intel Core Solo and Intel Core Duo processors support
base level functionality identified by version ID of 1. Processors based on Intel Core microarchitecture support, at
a minimum, the base level functionality of architectural performance monitoring. Intel Core 2 Duo processor T
7700 and newer processors based on Intel Core microarchitecture support both the base level functionality and
enhanced architectural performance monitoring identified by version ID of 2.
45 nm and 32 nm Intel Atom processors and Intel Atom processors based on the Silvermont microarchitecture
support the functionality provided by versionID 1, 2, and 3; CPUID.0AH:EAX[7:0] reports versionID = 3 to indicate
the aggregate of architectural performance monitoring capabilities. Intel Atom processors based on the Airmont
microarchitecture support the same performance monitoring capabilities as those based on the Silvermont micro-
architecture.
Intel Core processors and related Intel Xeon processor families based on the Nehalem through Broadwell microar-
chitectures support version ID 1, 2, and 3. Intel processors based on the Skylake microarchitecture support
versionID 4.
Next generation Intel Atom processors is based on the Goldmont microarchitecture. Intel processors based on the
Goldmont microarchitecture support versionID 4.
18.2.1
Architectural Performance Monitoring Version 1
Configuring an architectural performance monitoring event involves programming performance event select regis-
ters. There are a finite number of performance event select MSRs (IA32_PERFEVTSELx MSRs). The result of a
performance monitoring event is reported in a performance monitoring counter (IA32_PMCx MSR). Performance
monitoring counters are paired with performance monitoring select registers.
Performance monitoring select registers and counters are architectural in the following respects:
•
Bit field layout of IA32_PERFEVTSELx is consistent across microarchitectures.
•
Addresses of IA32_PERFEVTSELx MSRs remain the same across microarchitectures.
•
Addresses of IA32_PMC MSRs remain the same across microarchitectures.
•
Each logical processor has its own set of IA32_PERFEVTSELx and IA32_PMCx MSRs. Configuration facilities and
counters are not shared between logical processors sharing a processor core.
Architectural performance monitoring provides a CPUID mechanism for enumerating the following information: