Vol. 3B 18-99

PERFORMANCE MONITORING

18.15.7.5   Other DS Mechanism Implications

The DS mechanism is not available in the SMM. It is disabled on transition to the SMM mode. Similarly the DS 
mechanism is disabled on the generation of a machine check exception and is cleared on processor RESET and 
INIT. 
The DS mechanism is available in real address mode.

18.15.8 Operating 

System 

Implications

The DS mechanism can be used by the operating system as a debugging extension to facilitate failure analysis. 
When using this facility, a 25 to 30 times slowdown can be expected due to the effects of the trace store occurring 
on every taken branch. 
Depending upon intended usage, the instruction pointers that are part of the branch records or the PEBS records 
need to have an association with the corresponding process. One solution requires the ability for the DS specific 
operating system module to be chained to the context switch. A separate buffer can then be maintained for each 
process of interest and the MSR pointing to the configuration area saved and setup appropriately on each context 
switch. 
If the BTS facility has been enabled, then it must be disabled and state stored on transition of the system to a sleep 
state in which processor context is lost. The state must be restored on return from the sleep state.
It is required that an interrupt gate be used for the DS interrupt as opposed to a trap gate to prevent the generation 
of an endless interrupt loop.
Pages that contain buffers must have mappings to the same physical address for all processes/logical processors, 
such that any change to CR3 will not change DS addresses. If this requirement cannot be satisfied (that is, the 
feature is enabled on a per thread/process basis), then the operating system must ensure that the feature is 
enabled/disabled appropriately in the context switch code.

18.16  PERFORMANCE MONITORING AND INTEL HYPER-THREADING 

TECHNOLOGY IN PROCESSORS BASED ON INTEL NETBURST

®

 

MICROARCHITECTURE

The performance monitoring capability of processors based on Intel NetBurst microarchitecture and supporting 
Intel Hyper-Threading Technology is similar to that described in Section 18.15. However, the capability is extended 
so that:

•

Performance counters can be programmed to select events qualified by logical processor IDs. 

•

Performance monitoring interrupts can be directed to a specific logical processor within the physical processor. 

The sections below describe performance counters, event qualification by logical processor ID, and special purpose 
bits in ESCRs/CCCRs. They also describe MSR_PEBS_ENABLE, MSR_PEBS_MATRIX_VERT, and 
MSR_TC_PRECISE_EVENT. 

18.16.1 ESCR 

MSRs 

Figure 18-47 shows the layout of an ESCR MSR in processors supporting Intel Hyper-Threading Technology. 
The functions of the flags and fields are as follows:

•

T1_USR flag, bit 0 — When set, events are counted when thread 1 (logical processor 1) is executing at a 
current privilege level (CPL) of 1, 2, or 3. These privilege levels are generally used by application code and 
unprotected operating system code.