10-46 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

Logical x2APIC ID = [(x2APIC ID[19:4] « 16) | (1 « x2APIC ID[3:0])]

The use of the lowest 4 bits in the x2APIC ID implies that at least 16 APIC IDs are reserved for logical processors 
within a socket in multi-socket configurations. If more than 16 APIC IDS are reserved for logical processors in a 
socket/package then multiple cluster IDs can exist within the package. 
The LDR initialization occurs whenever the x2APIC mode is enabled (see Section 10.12.5).

10.12.11 SELF IPI Register

SELF IPIs are used extensively by some system software. The x2APIC architecture introduces a new register inter-
face. This new register is dedicated to the purpose of sending self-IPIs with the intent of enabling a highly opti-
mized path for sending self-IPIs. 
Figure 10-30 provides the layout of the SELF IPI register. System software only specifies the vector associated with 
the interrupt to be sent. The semantics of sending a self-IPI via the SELF IPI register are identical to sending a self 
targeted edge triggered fixed interrupt with the specified vector. Specifically the semantics are identical to the 
following settings for an inter-processor interrupt sent via the ICR - Destination Shorthand (ICR[19:18] = 01 
(Self)), Trigger Mode (ICR[15] = 0 (Edge)), Delivery Mode (ICR[10:8] = 000 (Fixed)), Vector (ICR[7:0] = Vector).

The SELF IPI register is a write-only register. A RDMSR instruction with address of the SELF IPI register causes a 
general-protection exception. 
The handling and prioritization of a self-IPI sent via the SELF IPI register is architecturally identical to that for an 
IPI sent via the ICR from a legacy xAPIC unit. Specifically the state of the interrupt would be tracked via the Inter-
rupt Request Register (IRR) and In Service Register (ISR) and Trigger Mode Register (TMR) as if it were received 
from the system bus. Also sending the IPI via the Self Interrupt Register ensures that interrupt is delivered to the 
processor core. Specifically completion of the WRMSR instruction to the SELF IPI register implies that the interrupt 
has been logged into the IRR. As expected for edge triggered interrupts, depending on the processor priority and 
readiness to accept interrupts, it is possible that interrupts sent via the SELF IPI register or via the ICR with iden-
tical vectors can be combined.

10.13  APIC BUS MESSAGE FORMATS

This section describes the message formats used when transmitting messages on the serial APIC bus. The informa-
tion described here pertains only to the Pentium and P6 family processors.

10.13.1  Bus Message Formats

The local and I/O APICs transmit three types of messages on the serial APIC bus: EOI message, short message, 
and non-focused lowest priority message. The purpose of each type of message and its format are described below.

Figure 10-30.  SELF IPI register

MSR Address: 083FH

31

8 7

0

Reserved

Vector