Vol. 3A 8-3

MULTIPLE-PROCESSOR MANAGEMENT

8.1.2 Bus 

Locking

Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory 
operations to lock the system bus or equivalent link. While this output signal is asserted, requests from other 
processors or bus agents for control of the bus are blocked. Software can specify other occasions when the LOCK 
semantics are to be followed by prepending the LOCK prefix to an instruction.
In the case of the Intel386, Intel486, and Pentium processors, explicitly locked instructions will result in the asser-
tion of the LOCK# signal. It is the responsibility of the hardware designer to make the LOCK# signal available in 
system hardware to control memory accesses among processors.
For the P6 and more recent processor families, if the memory area being accessed is cached internally in the 
processor, the LOCK# signal is generally not asserted; instead, locking is only applied to the processor’s caches 
(see Section 8.1.4, “Effects of a LOCK Operation on Internal Processor Caches”).

8.1.2.1  

Automatic Locking

The operations on which the processor automatically follows the LOCK semantics are as follows:

•

When executing an XCHG instruction that references memory.

•

When setting the B (busy) flag of a TSS descriptor — The processor tests and sets the busy flag in the 
type field of the TSS descriptor when switching to a task. To ensure that two processors do not switch to the 
same task simultaneously, the processor follows the LOCK semantics while testing and setting this flag.

•

When updating segment descriptors — When loading a segment descriptor, the processor will set the 
accessed flag in the segment descriptor if the flag is clear. During this operation, the processor follows the 
LOCK semantics so that the descriptor will not be modified by another processor while it is being updated. For 
this action to be effective, operating-system procedures that update descriptors should use the following steps:
— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is not-

present, and specify a value for the type field that indicates that the descriptor is being updated.

— Update the fields of the segment descriptor. (This operation may require several memory accesses; 

therefore, locked operations cannot be used.)

— Use a locked operation to modify the access-rights byte to indicate that the segment descriptor is valid and 

present.

•

The Intel386 processor always updates the accessed flag in the segment descriptor, whether it is clear or not. 
The Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors only update this flag if it is not already 
set.

•

When updating page-directory and page-table entries — When updating page-directory and page-table 
entries, the processor uses locked cycles to set the accessed and dirty flag in the page-directory and page-table 
entries.

•

Acknowledging interrupts — After an interrupt request, an interrupt controller may use the data bus to send 
the interrupt’s vector to the processor. The processor follows the LOCK semantics during this time to ensure 
that no other data appears on the data bus while the vector is being transmitted.

8.1.2.2  

Software Controlled Bus Locking

To explicitly force the LOCK semantics, software can use the LOCK prefix with the following instructions when they 
are used to modify a memory location. An invalid-opcode exception (#UD) is generated when the LOCK prefix is 
used with any other instruction or when no write operation is made to memory (that is, when the destination 
operand is in a register).

•

The bit test and modify instructions (BTS, BTR, and BTC).

•

The exchange instructions (XADD, CMPXCHG, and CMPXCHG8B). 

•

The LOCK prefix is automatically assumed for XCHG instruction.

•

The following single-operand arithmetic and logical instructions: INC, DEC, NOT, and NEG.

•

The following two-operand arithmetic and logical instructions: ADD, ADC, SUB, SBB, AND, OR, and XOR.