34-6 Vol. 3C

SYSTEM MANAGEMENT MODE

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Debug registers DR0 through DR3.

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The x87 FPU registers.

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The MTRRs.

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Control register CR2.

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The model-specific registers (for the P6 family and Pentium processors) or test registers TR3 through TR7 (for 
the Pentium and Intel486 processors).

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The state of the trap controller.

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The machine-check architecture registers.

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The APIC internal interrupt state (ISR, IRR, etc.).

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The microcode update state.

If an SMI is used to power down the processor, a power-on reset will be required before returning to SMM, which 
will reset much of this state back to its default values. So an SMI handler that is going to trigger power down should 
first read these registers listed above directly, and save them (along with the rest of RAM) to nonvolatile storage. 
After the power-on reset, the continuation of the SMI handler should restore these values, along with the rest of 
the system's state. Anytime the SMI handler changes these registers in the processor, it must also save and restore 
them.

NOTES

A small subset of the MSRs (such as, the time-stamp counter and performance-monitoring 
counters) are not arbitrarily writable and therefore cannot be saved and restored. SMM-based 
power-down and restoration should only be performed with operating systems that do not use or 
rely on the values of these registers. 
Operating system developers should be aware of this fact and insure that their operating-system 
assisted power-down and restoration software is immune to unexpected changes in these register 
values.

34.4.1.1   SMRAM State Save Map and Intel 64 Architecture

When the processor initially enters SMM, it writes its state to the state save area of the SMRAM. The state save area 
on an Intel 64 processor at [SMBASE + 8000H + 7FFFH] and extends to [SMBASE + 8000H + 7C00H]. 
Support for Intel 64 architecture is reported by CPUID.80000001:EDX[29] = 1. The layout of the SMRAM state save 
map is shown in Table 34-3. 
Additionally, the SMRAM state save map shown in Table 34-3 also applies to processors with the following CPUID 
signatures listed in Table 34-2, irrespective of the value in CPUID.80000001:EDX[29].

Table 34-2.   Processor Signatures and 64-bit SMRAM State Save Map Format

DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_17H

Intel Xeon Processor 5200, 5400 series, Intel Core 2 Quad processor Q9xxx, Intel Core 2 Duo 

processors E8000, T9000,

06_0FH

Intel Xeon Processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad, Intel Core 2 Extreme, 

Intel Core 2 Duo processors, Intel Pentium dual-core processors

06_1CH

45 nm Intel® Atom™ processors