Vol. 3C 31-13
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
Many VMCS fields are architected to extend transparently on processors supporting Intel 64 architecture (64 bits
on processors that support Intel 64 architecture, 32 bits on processors that do not). Some VMCS fields are 64-bits
wide regardless of whether the processor supports Intel 64 architecture or is in IA-32e mode.
31.9.2.1 Natural-Width VMCS Fields
Many VMCS fields operate using natural width. Such fields return (on reads) and set (on writes) 32-bits when oper-
ating in 32-bit mode and 64-bits when operating in 64-bit mode. For the most part, these fields return the naturally
expected data widths. The “Guest RIP” field in the VMCS guest-state area is an example of this type of field.
31.9.2.2 64-Bit VMCS Fields
Unlike natural width fields, these fields are fixed to 64-bit width on all processors. When in 64-bit mode, reads of
these fields return 64-bit wide data and writes to these fields write 64-bits. When outside of 64-bit mode, reads of
these fields return the low 32-bits and writes to these fields write the low 32-bits and zero the upper 32-bits.
Should a non-IA-32e mode host require access to the upper 32-bits of these fields, a separate VMCS encoding is
used when issuing VMREAD/VMWRITE instructions.
The VMCS control field “MSR bitmap address” (which contains the physical address of a region of memory which
specifies which MSR accesses should generate VM-exits) is an example of this type of field. Specifying encoding
00002004H to VMREAD returns the lower 32-bits to non-IA-32e mode hosts and returns 64-bits to 64-bit hosts.
The separate encoding 00002005H returns only the upper 32-bits.
31.9.3
IA-32e Mode Hosts
An IA-32e mode host is required to support 64-bit guest environments. Because activating IA-32e mode currently
requires that paging be disabled temporarily and VMX entry requires paging to be enabled, IA-32e mode must be
enabled before entering VMX operation. For this reason, it is not possible to toggle in and out of IA-32e mode in a
VMM.
Section 31.5 describes the steps required to launch a VMM. An IA-32e mode host is also required to set the “host
address-space size” VMCS VM-exit control to 1. The value of this control is then loaded in the IA32_EFER.LME/LMA
and CS.L bits on each VM exit. This establishes a 64-bit host environment as execution transfers to the VMM entry
point. At a minimum, the entry point is required to be in a 64-bit code segment. Subsequently, the VMM can, if it
chooses, switch to 32-bit compatibility mode on a code-segment basis (see Section 31.9.1). Note, however, that
VMX instructions other than VMCALL and VMFUNC are not supported in compatibility mode; they generate an
invalid opcode exception if used.
The following VMCS controls determine the value of IA32_EFER when a VM exit occurs: the “host address-space
size” control (described above), the “load IA32_EFER” VM-exit control, the “VM-exit MSR-load count,” and the “VM-
exit MSR-load address” (see Section 27.3).
If the “load IA32_EFER” VM-exit control is 1, the value of the LME and LMA bits in the IA32_EFER field in the host-
state area must be the value of the “host address-space size” VM-exit control.
The loading of IA32_EFER.LME/LMA and CS.L bits established by the “host address-space size” control precede any
loading of the IA32_EFER MSR due from the VM-exit MSR-load area. If IA32_EFER is specified in the VM-exit MSR-
load area, the value of the LME bit in the load image of IA32_EFER should match the setting of the “host address-
space size” control. Otherwise the attempt to modify the LME bit (while paging is enabled) will lead to a VMX-abort.
However, IA32_EFER.LMA is always set by the processor to equal IA32_EFER.LME & CR0.PG; the value specified
for LMA in the load image of the IA32_EFER MSR is ignored. For these and performance reasons, VMM writers may
choose to not use the VM-exit/entry MSR-load/save areas for IA32_EFER.
On a VMM teardown, VMX operation should be exited before deactivating IA-32e mode if the latter is required.
31.9.4
IA-32e Mode Guests
A 32-bit guest can be launched by either IA-32e-mode hosts or non-IA-32e-mode hosts. A 64-bit guests can only
be launched by a IA-32e-mode host.