Vol. 3B 18-117

PERFORMANCE MONITORING

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PC (pin control) flag (bit 19) — When set, the processor toggles the PMi pins and increments the counter 
when performance-monitoring events occur; when clear, the processor toggles the PMi pins when the counter 
overflows. The toggling of a pin is defined as assertion of the pin for a single bus clock followed by deassertion.

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INT (APIC interrupt enable) flag (bit 20) — When set, the processor generates an exception through its 
local APIC on counter overflow.

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EN (Enable Counters) Flag (bit 22) — This flag is only present in the PerfEvtSel0 MSR. When set, 
performance counting is enabled in both performance-monitoring counters; when clear, both counters are 
disabled.

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INV (invert) flag (bit 23) — When set, inverts the counter-mask (CMASK) comparison, so that both greater 
than or equal to and less than comparisons can be made (0: greater than or equal; 1: less than). Note if 
counter-mask is programmed to zero, INV flag is ignored.

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Counter mask (CMASK) field (bits 24 through 31) — When nonzero, the processor compares this mask to 
the number of events counted during a single cycle. If the event count is greater than or equal to this mask, the 
counter is incremented by one. Otherwise the counter is not incremented. This mask can be used to count 
events only if multiple occurrences happen per clock (for example, two or more instructions retired per clock). 
If the counter-mask field is 0, then the counter is incremented each cycle by the number of events that 
occurred that cycle.

18.22.2  PerfCtr0 and PerfCtr1 MSRs

The performance-counter MSRs (PerfCtr0 and PerfCtr1) contain the event or duration counts for the selected 
events being counted. The RDPMC instruction can be used by programs or procedures running at any privilege level 
and in virtual-8086 mode to read these counters. The PCE flag in control register CR4 (bit 8) allows the use of this 
instruction to be restricted to only programs and procedures running at privilege level 0.
The RDPMC instruction is not serializing or ordered with other instructions. Thus, it does not necessarily wait until 
all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may 
begin execution before the RDPMC instruction operation is performed.
Only the operating system, executing at privilege level 0, can directly manipulate the performance counters, using 
the RDMSR and WRMSR instructions. A secure operating system would clear the PCE flag during system initializa-
tion to disable direct user access to the performance-monitoring counters, but provide a user-accessible program-
ming interface that emulates the RDPMC instruction.
The WRMSR instruction cannot arbitrarily write to the performance-monitoring counter MSRs (PerfCtr0 and 
PerfCtr1). Instead, the lower-order 32 bits of each MSR may be written with any value, and the high-order 8 bits 
are sign-extended according to the value of bit 31. This operation allows writing both positive and negative values 
to the performance counters.

18.22.3  Starting and Stopping the Performance-Monitoring Counters

The performance-monitoring counters are started by writing valid setup information in the PerfEvtSel0 and/or 
PerfEvtSel1 MSRs and setting the enable counters flag in the PerfEvtSel0 MSR. If the setup is valid, the counters 
begin counting following the execution of a WRMSR instruction that sets the enable counter flag. The counters can 
be stopped by clearing the enable counters flag or by clearing all the bits in the PerfEvtSel0 and PerfEvtSel1 MSRs. 
Counter 1 alone can be stopped by clearing the PerfEvtSel1 MSR.