10-16 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

The ESR is a write/read register. Before attempt to read from the ESR, software should first write to it. (The value 
written does not affect the values read subsequently; only zero may be written in x2APIC mode.) This write clears 
any previously logged errors and updates the ESR with any errors detected since the last write to the ESR. This 
write also rearms the APIC error interrupt triggering mechanism.
The LVT Error Register (see Section 10.5.1) allows specification of the vector of the interrupt to be delivered to the 
processor core when APIC error is detected. The register also provides a means of masking an APIC-error interrupt. 
This masking only prevents delivery of APIC-error interrupts; the APIC continues to record errors in the ESR.

10.5.4 APIC 

Timer

The local APIC unit contains a 32-bit programmable timer that is available to software to time events or operations. 
This timer is set up by programming four registers: the divide configuration register (see Figure 10-10), the initial-
count and current-count registers (see Figure 10-11), and the LVT timer register (see Figure 10-8). 
If CPUID.06H:EAX.ARAT[bit 2] = 1, the processor’s APIC timer runs at a constant rate regardless of P-state transi-
tions and it continues to run at the same rate in deep C-states.
If CPUID.06H:EAX.ARAT[bit 2] = 0 or if CPUID 06H is not supported, the APIC timer may temporarily stop while the 
processor is in deep C-states or during transitions caused by Enhanced Intel SpeedStep® Technology.

The APIC timer frequency will be the processor’s bus clock or core crystal clock frequency (when TSC/core crystal 
clock ratio is enumerated in CPUID leaf 0x15) divided by the value specified in the divide configuration register.
The timer can be configured through the timer LVT entry for one-shot or periodic operation. In one-shot mode, the 
timer is started by programming its initial-count register. The initial count value is then copied into the current-
count register and count-down begins. After the timer reaches zero, an timer interrupt is generated and the timer 
remains at its 0 value until reprogrammed. 
In periodic mode, the current-count register is automatically reloaded from the initial-count register when the 
count reaches 0 and a timer interrupt is generated, and the count-down is repeated. If during the count-down 

Figure 10-10.  Divide Configuration Register

 

Figure 10-11.  Initial Count and Current Count Registers

Address: FEE0 03E0H
Value after reset: 0H

0

Divide Value (bits 0, 1 and 3)

000: Divide by 2
001: Divide by 4
010: Divide by 8
011: Divide by 16

100: Divide by 32
101: Divide by 64
110: Divide by 128
111: Divide by 1

31

0

Reserved

1

2

3

4

31

0

Initial Count

Address: Initial Count

Value after reset: 0H

Current Count

Current Count FEE0 0390H

FEE0 0380H