36-20 Vol. 3C
INTEL® PROCESSOR TRACE
36.2.7.5 IA32_RTIT_ADDRn_A and IA32_RTIT_ADDRn_B MSRs
The role of the IA32_RTIT_ADDRn_A/B register pairs, for each n, is determined by the corresponding ADDRn_CFG
fields in IA32_RTIT_CTL (see Section 36.2.7.2). The number of these register pairs is enumerated by
CPUID.(EAX=14H, ECX=1):EAX.RANGECNT[2:0].
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Processors that enumerate support for 1 range support:
IA32_RTIT_ADDR0_A, IA32_RTIT_ADDR0_B
Table 36-7. IA32_RTIT_STATUS MSR
Position
Bit Name
At Reset
Bit Description
0
FilterEn
0
This bit is written by the processor, and indicates that tracing is allowed for the current IP,
see Section 36.2.5.5. Writes are ignored.
1
ContextEn
0
The processor sets this bit to indicate that tracing is allowed for the current context. See
Section 36.2.5.3. Writes are ignored.
2
TriggerEn
0
The processor sets this bit to indicate that tracing is enabled. See Section 36.2.5.2. Writes are
ignored.
3
Reserved
0
Must be 0.
4
Error
0
The processor sets this bit to indicate that an operational error has been encountered. When
this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details, see
“ToPA Errors” in Section 36.2.6.2.
When TraceEn is cleared, software can write this bit. Once it is set, only software can clear it.
It is not recommended that software ever set this bit, except in cases where it is restoring a
prior saved state.
5
Stopped
0
The processor sets this bit to indicate that a ToPA Stop condition has been encountered.
When this bit is set, TriggerEn is cleared to 0 and packet generation is disabled. For details,
see “ToPA STOP” in Section 36.2.6.2.
When TraceEn is cleared, software can write this bit. Once it is set, only software can clear it.
It is not recommended that software ever set this bit, except in cases where it is restoring a
prior saved state.
31:6
Reserved
0
Must be 0.
48:32
PacketByteCnt 0
This field is written by the processor, and holds a count of packet bytes that have been sent
out. The processor also uses this field to determine when the next PSB packet should be
inserted. Note that the processor may clear or modify this field at any time while
IA32_RTIT_CTL.TraceEn=1. It will have a stable value when IA32_RTIT_CTL.TraceEn=0.
See Section 36.4.2.17 for details.
63:49
Reserved
0
Must be 0.