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A-4 Vol. 3D

VMX CAPABILITY REPORTING FACILITY

If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_PROCBASED_CTLS MSR (index 48EH)
reports on the allowed settings of all of the primary processor-based VM-execution controls:

•

Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X to be 0 if bit X in the MSR
is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0. There are no exceptions.

•

Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control X to be 1 if bit 32+X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

It is necessary for software to consult only one of the capability MSRs to determine the allowed settings of the
primary processor-based VM-execution controls:

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If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the allowed settings of the primary
processor-based VM-execution controls is contained in the IA32_VMX_PROCBASED_CTLS MSR. (The
IA32_VMX_TRUE_PROCBASED_CTLS MSR is not supported.)

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If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the allowed settings of the processor-
based VM-execution controls is contained in the IA32_VMX_TRUE_PROCBASED_CTLS MSR. Assuming that
software knows that the default1 class of processor-based VM-execution controls contains bits 1, 4–6, 8, 13–
16, and 26, there is no need for software to consult the IA32_VMX_PROCBASED_CTLS MSR.

A.3.3

Secondary Processor-Based VM-Execution Controls

The IA32_VMX_PROCBASED_CTLS2 MSR (index 48BH) reports on the allowed settings of the secondary processor-
based VM-execution controls (see Section 24.6.2). VM entries perform the following checks:

•

Bits 31:0 indicate the allowed 0-settings of these controls. These bits are always 0. This fact indicates that
VM entry allows each bit of the secondary processor-based VM-execution controls to be 0 (reserved bits must
be 0)

•

Bits 63:32 indicate the allowed 1-settings of these controls; the 1-setting is not allowed for any reserved bit.
VM entry allows control X (bit X of the secondary processor-based VM-execution controls) to be 1 if bit 32+X in
the MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X and the “activate secondary
controls” primary processor-based VM-execution control are both 1.

The IA32_VMX_PROCBASED_CTLS2 MSR exists only on processors that support the 1-setting of the “activate
secondary controls” VM-execution control (only if bit 63 of the IA32_VMX_PROCBASED_CTLS MSR is 1).

A.4 VM-EXIT

CONTROLS

The IA32_VMX_EXIT_CTLS MSR (index 483H) reports on the allowed settings of most of the VM-exit controls (see
Section 24.7.1):

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Bits 31:0 indicate the allowed 0-settings of these controls. VM entry allows control X (bit X of the VM-exit
controls) to be 0 if bit X in the MSR is cleared to 0; if bit X in the MSR is set to 1, VM entry fails if control X is 0.
Exceptions are made for the VM-exit controls in the default1 class (see Appendix A.2). These are bits 0–8, 10,
11, 13, 14, 16, and 17; the corresponding bits of the IA32_VMX_EXIT_CTLS MSR are always read as 1. The
treatment of these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any VM-exit control in the default1 class

is 0.

— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_EXIT_CTLS MSR (see below)

reports which of the VM-exit controls in the default1 class can be 0 on VM entry.

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Bits 63:32 indicate the allowed 1-settings of these controls. VM entry allows control 32+X to be 1 if bit X in the
MSR is set to 1; if bit 32+X in the MSR is cleared to 0, VM entry fails if control X is 1.

If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the IA32_VMX_TRUE_EXIT_CTLS MSR (index 48FH) reports on
the allowed settings of all of the VM-exit controls:

•