Vol. 3C 32-7

VIRTUALIZATION OF SYSTEM RESOURCES

the VMM caused an address-space change and flushed the processor’s TLB, the VMM can simply re-execute the 
faulting instruction. 
The remaining steps assume that PS = 0 in the active and guest PDEs.

8. Consult the active PTE, which can be located using the next 10 bits of the faulting address (bits 21–12) and the 

physical page-table base address in the active PDE. The active PTE is the source of the fault if it is marked not-
present or if its R/W bit and U/S bits are inconsistent with the attempted guest access (the guest privilege level 
and the values of CR0.WP and CR4.SMEP should also be taken into account).

9. If the active PTE is not the source of the fault, then the fault has resulted from an inconsistency between the 

active page-table hierarchy and the processor’s TLB. Since the transition to the VMM caused an address-space 
change and flushed the processor’s TLB, the VMM simply re-executes the faulting instruction.
The remaining steps assume that the active PTE is the source of the fault.

10. Consult the corresponding guest PTE using the same 10 bits from the faulting address and the physical address 

that correspond to the guest page-table base address in the guest PDE. If the guest PTE would cause a page 
fault (it is marked not-present), the raise a page fault to the guest operating system. 
The following steps assume that the guest PTE would not have caused a page fault.

11. If the guest PTE contains, as page base address, a physical address that is not valid for the virtual machine 

being supported; then raise a machine check (or some other abort) to the guest operating system. 
The following steps assume that the address in the guest PTE is valid for the virtual machine.

12. If the active PTE is marked not-present, then set the active PTE to correspond to guest PTE:

a. Set the page base address in the active PTE to be the physical address that corresponds to the guest page 

base address in the guest PTE.

b. Set the P, U/S, and PS bits in the active PTE to be identical to those in the guest PTE.
c. Set the PWT, PCD, and G bits according to the policy of the VMM.
d. Set A = 1 in the guest PTE.
e. If D = 1 in the guest PTE, then set the R/W bit in the active PTE as in the guest PTE.
f.

If D = 0 in the guest PTE and the attempted access is a write, then set R/W in the active PTE as in the guest 
PTE and set D = 1 in the guest PTE.

g. If D = 0 in the guest PTE and the attempted access is not a write, then set R/W = 0 in the active PTE.
h. After modifying the active PTE, re-execute the faulting instruction. 
The remaining steps assume that the active PTE is already marked present.

13. If the attempted access is a write, D = 0 (not dirty) in the guest PTE and the active PTE has caused a fault 

solely because it has R/W = 0 (read-only); then set R/W in the active PTE as in the guest PTE, set D = 1 in the 
guest PTE and re-execute the faulting instruction.

14. If none of the above cases apply, then raise a page fault of the guest operating system.

32.3.5.3   Response to Uses of INVLPG

Operating-systems can use INVLPG to flush entries from the TLB. This instruction takes a linear address as an 
operand and software expects any cached translations for the address to be flushed. A VMM should set the 
processor-based VM-execution control “INVLPG exiting” to 1 so that any attempts by a privileged guest to execute 
INVLPG will trap to the VMM. The VMM can then modify the active page-table hierarchy to emulate the desired 
effect of the INVLPG. 
The following steps are performed. Note that these steps are performed only if the guest invocation of INVLPG 
would not fault and only if the guest software is running at privilege level 0:
1. Locate the relevant active PDE using the upper 10 bits of the operand address and the current value of CR3. If 

the PDE refers to a 4-MByte page (PS = 1), then set P = 0 in the PDE.

2. If the PDE is marked present and refers to a page table (PS = 0), locate the relevant active PTE using the next 

10 bits of the operand address (bits 21–12) and the page-table base address in the PDE. Set P = 0 in the PTE.