14-20 Vol. 3B

POWER AND THERMAL MANAGEMENT

14.7.1 

Catastrophic Shutdown Detector

P6 family processors introduced a thermal sensor that acts as a catastrophic shutdown detector. This catastrophic 
shutdown detector was also implemented in Pentium 4, Intel Xeon and Pentium M processors. It is always enabled. 
When processor core temperature reaches a factory preset level, the sensor trips and processor execution is halted 
until after the next reset cycle.

14.7.2 Thermal 

Monitor

Pentium 4, Intel Xeon and Pentium M processors introduced a second temperature sensor that is factory-calibrated 
to trip when the processor’s core temperature crosses a level corresponding to the recommended thermal design 
envelop. The trip-temperature of the second sensor is calibrated below the temperature assigned to the cata-
strophic shutdown detector. 

14.7.2.1   Thermal Monitor 1

The Pentium 4 processor uses the second temperature sensor in conjunction with a mechanism called Thermal 
Monitor 1 (TM1) to control the core temperature of the processor. TM1 controls the processor’s temperature by 
modulating the duty cycle of the processor clock. Modulation of duty cycles is processor model specific. Note that 
the processors STPCLK# pin is not used here; the stop-clock circuitry is controlled internally.
Support for TM1 is indicated by CPUID.1:EDX.TM[bit 29] = 1.
TM1 is enabled by setting the thermal-monitor enable flag (bit 3) in IA32_MISC_ENABLE [see Chapter 35, “Model-
Specific Registers (MSRs),”]. Following a power-up or reset, the flag is cleared, disabling TM1. BIOS is required to 
enable only one automatic thermal monitoring modes. Operating systems and applications must not disable the 
operation of these mechanisms.

14.7.2.2   Thermal Monitor 2

An additional automatic thermal protection mechanism, called Thermal Monitor 2 (TM2), was introduced in the 
Intel Pentium M processor and also incorporated in newer models of the Pentium 4 processor family. Intel Core Duo 
and Solo processors, and Intel Core 2 Duo processor family all support TM1 and TM2. TM2 controls the core 
temperature of the processor by reducing the operating frequency and voltage of the processor and offers a higher 
performance level for a given level of power reduction than TM1.
TM2 is triggered by the same temperature sensor as TM1. The mechanism to enable TM2 may be implemented 
differently across various IA-32 processor families with different CPUID signatures in the family encoding value, but 
will be uniform within an IA-32 processor family. 
Support for TM2 is indicated by CPUID.1:ECX.TM2[bit 8] = 1.

14.7.2.3   Two Methods for Enabling TM2

On processors with CPUID family/model/stepping signature encoded as 0x69n or 0x6Dn (early Pentium M proces-
sors), TM2 is enabled if the TM_SELECT flag (bit 16) of the MSR_THERM2_CTL register is set to 1 (Figure 14-21) 
and bit 3 of the IA32_MISC_ENABLE register is set to 1. 
Following a power-up or reset, the TM_SELECT flag may be cleared. BIOS is required to enable either TM1 or TM2. 
Operating systems and applications must not disable mechanisms that enable TM1 or TM2. If bit 3 of the 
IA32_MISC_ENABLE register is set and TM_SELECT flag of the MSR_THERM2_CTL register is cleared, TM1 is 
enabled.