Vol. 3A 7-5

TASK MANAGEMENT

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CR3 control register field — Contains the base physical address of the page directory to be used by the task. 
Control register CR3 is also known as the page-directory base register (PDBR).

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Privilege level-0, -1, and -2 stack pointer fields — These stack pointers consist of a logical address made 
up of the segment selector for the stack segment (SS0, SS1, and SS2) and an offset into the stack (ESP0, 
ESP1, and ESP2). Note that the values in these fields are static for a particular task; whereas, the SS and ESP 
values will change if stack switching occurs within the task.

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T (debug trap) flag (byte 100, bit 0) — When set, the T flag causes the processor to raise a debug exception 
when a task switch to this task occurs (see Section 17.3.1.5, “Task-Switch Exception Condition”).

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I/O map base address field — Contains a 16-bit offset from the base of the TSS to the I/O permission bit 
map and interrupt redirection bitmap. When present, these maps are stored in the TSS at higher addresses. 
The I/O map base address points to the beginning of the I/O permission bit map and the end of the interrupt 
redirection bit map. See Chapter 18, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software 
Developer’s Manual, Volume 1, for more information about the I/O permission bit map. See Section 20.3, 
“Interrupt and Exception Handling in Virtual-8086 Mode,” for a detailed description of the interrupt redirection 
bit map.

If paging is used: 

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Avoid placing a page boundary in the part of the TSS that the processor reads during a task switch (the first 104 
bytes). The processor may not correctly perform address translations if a boundary occurs in this area. During 
a task switch, the processor reads and writes into the first 104 bytes of each TSS (using contiguous physical 
addresses beginning with the physical address of the first byte of the TSS). So, after TSS access begins, if part 
of the 104 bytes is not physically contiguous, the processor will access incorrect information without generating 
a page-fault exception.

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Pages corresponding to the previous task’s TSS, the current task’s TSS, and the descriptor table entries for 
each all should be marked as read/write. 

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Task switches are carried out faster if the pages containing these structures are present in memory before the 
task switch is initiated.

7.2.2 TSS 

Descriptor

The TSS, like all other segments, is defined by a segment descriptor. Figure 7-3 shows the format of a TSS 
descriptor. TSS descriptors may only be placed in the GDT; they cannot be placed in an LDT or the IDT. 
An attempt to access a TSS using a segment selector with its TI flag set (which indicates the current LDT) causes 
a general-protection exception (#GP) to be generated during CALLs and JMPs; it causes an invalid TSS exception 
(#TS) during IRETs. A general-protection exception is also generated if an attempt is made to load a segment 
selector for a TSS into a segment register.
The busy flag (B) in the type field indicates whether the task is busy. A busy task is currently running or suspended. 
A type field with a value of 1001B indicates an inactive task; a value of 1011B indicates a busy task. Tasks are not 
recursive. The processor uses the busy flag to detect an attempt to call a task whose execution has been inter-
rupted. To insure that there is only one busy flag is associated with a task, each TSS should have only one TSS 
descriptor that points to it.