6-6 Vol. 3A

INTERRUPT AND EXCEPTION HANDLING

Architectures,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more infor-
mation about the P6 family processors’ microarchitecture and its support for out-of-order instruction execution.
Note that the Pentium processor and earlier IA-32 processors also perform varying amounts of prefetching and 
preliminary decoding. With these processors as well, exceptions and interrupts are not signaled until actual “in-
order” execution of the instructions. For a given code sample, the signaling of exceptions occurs uniformly when 
the code is executed on any family of IA-32 processors (except where new exceptions or new opcodes have been 
defined).

6.7 

NONMASKABLE INTERRUPT (NMI)

The nonmaskable interrupt (NMI) can be generated in either of two ways:

•

External hardware asserts the NMI pin.

•

The processor receives a message on the system bus (Pentium 4, Intel Core Duo, Intel Core 2, Intel Atom, and 
Intel Xeon processors) or the APIC serial bus (P6 family and Pentium processors) with a delivery mode NMI.

When the processor receives a NMI from either of these sources, the processor handles it immediately by calling 
the NMI handler pointed to by interrupt vector number 2. The processor also invokes certain hardware conditions 
to insure that no other interrupts, including NMI interrupts, are received until the NMI handler has completed 
executing (see Section 6.7.1, “Handling Multiple NMIs”).
Also, when an NMI is received from either of the above sources, it cannot be masked by the IF flag in the EFLAGS 
register.
It is possible to issue a maskable hardware interrupt (through the INTR pin) to vector 2 to invoke the NMI interrupt 
handler; however, this interrupt will not truly be an NMI interrupt. A true NMI interrupt that activates the 
processor’s NMI-handling hardware can only be delivered through one of the mechanisms listed above.

6.7.1 

Handling Multiple NMIs

While an NMI interrupt handler is executing, the processor blocks delivery of subsequent NMIs until the next execu-
tion of the IRET instruction. This blocking of NMIs prevents nested execution of the NMI handler. It is recommended 
that the NMI interrupt handler be accessed through an interrupt gate to disable maskable hardware interrupts (see 
Section 6.8.1, “Masking Maskable Hardware Interrupts”). 
An execution of the IRET instruction unblocks NMIs even if the instruction causes a fault. For example, if the IRET 
instruction executes with EFLAGS.VM = 1 and IOPL of less than 3, a general-protection exception is generated (see 
Section 20.2.7, “Sensitive Instructions”). In such a case, NMIs are unmasked before the exception handler is 
invoked.

6.8 

ENABLING AND DISABLING INTERRUPTS

The processor inhibits the generation of some interrupts, depending on the state of the processor and of the IF and 
RF flags in the EFLAGS register, as described in the following sections.

6.8.1 

Masking Maskable Hardware Interrupts

The IF flag can disable the servicing of maskable hardware interrupts received on the processor’s INTR pin or 
through the local APIC (see Section 6.3.2, “Maskable Hardware Interrupts”). When the IF flag is clear, the 
processor inhibits interrupts delivered to the INTR pin or through the local APIC from generating an internal inter-
rupt request; when the IF flag is set, interrupts delivered to the INTR or through the local APIC pin are processed 
as normal external interrupts. 
The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pin or delivery mode NMI 
messages delivered through the local APIC, nor does it affect processor generated exceptions. As with the other 
flags in the EFLAGS register, the processor clears the IF flag in response to a hardware reset.