Vol. 3B 18-87

PERFORMANCE MONITORING

The RDPMC instruction is not serializing or ordered with other instructions. Thus, it does not necessarily wait until 
all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may 
begin execution before the RDPMC instruction operation is performed.
Only the operating system, executing at privilege level 0, can directly manipulate the performance counters, using 
the RDMSR and WRMSR instructions. A secure operating system would clear the PCE flag during system initializa-
tion to disable direct user access to the performance-monitoring counters, but provide a user-accessible program-
ming interface that emulates the RDPMC instruction.
Some uses of the performance counters require the counters to be preset before counting begins (that is, before 
the counter is enabled). This can be accomplished by writing to the counter using the WRMSR instruction. To set a 
counter to a specified number of counts before overflow, enter a 2s complement negative integer in the counter. 
The counter will then count from the preset value up to -1 and overflow. Writing to a performance counter in a 
Pentium 4 or Intel Xeon processor with the WRMSR instruction causes all 40 bits of the counter to be written.

18.15.3 CCCR 

MSRs

Each of the 18 performance counters has one CCCR MSR associated with it (see Table 18-63). The CCCRs control 
the filtering and counting of events as well as interrupt generation. Figure 18-45 shows the layout of an CCCR MSR. 
The functions of the flags and fields are as follows:

•

Enable flag, bit 12 — When set, enables counting; when clear, the counter is disabled. This flag is cleared on 
reset.

•

ESCR select field, bits 13 through 15 — Identifies the ESCR to be used to select events to be counted with 
the counter associated with the CCCR.

•

Compare flag, bit 18 — When set, enables filtering of the event count; when clear, disables filtering. The 
filtering method is selected with the threshold, complement, and edge flags.

•

Complement flag, bit 19 — Selects how the incoming event count is compared with the threshold value. 
When set, event counts that are less than or equal to the threshold value result in a single count being 
delivered to the performance counter; when clear, counts greater than the threshold value result in a count 
being delivered to the performance counter (see Section 18.15.5.2, “Filtering Events”). The complement flag is 
not active unless the compare flag is set.

•

Threshold field, bits 20 through 23 — Selects the threshold value to be used for comparisons. The 
processor examines this field only when the compare flag is set, and uses the complement flag setting to 
determine the type of threshold comparison to be made. The useful range of values that can be entered in this 
field depend on the type of event being counted (see Section 18.15.5.2, “Filtering Events”).

•

Edge flag, bit 24 — When set, enables rising edge (false-to-true) edge detection of the threshold comparison 
output for filtering event counts; when clear, rising edge detection is disabled. This flag is active only when the 
compare flag is set.

Figure 18-44.  Performance Counter (Pentium 4 and Intel Xeon Processors)

63

32

Reserved

31

0

Counter

39

Counter