Vol. 3B 17-39

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

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BTF (single-step on branches) flag (bit 1) — When set, the processor treats the TF flag in the EFLAGS 
register as a “single-step on branches” flag. See Section 17.4.3, “Single-Stepping on Branches.”

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PBi (performance monitoring/breakpoint pins) flags (bits 2 through 5) — When these flags are set, 
the performance monitoring/breakpoint pins on the processor (BP0#, BP1#, BP2#, and BP3#) report 
breakpoint matches in the corresponding breakpoint-address registers (DR0 through DR3). The processor 
asserts then deasserts the corresponding BPi# pin when a breakpoint match occurs. When a PBi flag is clear, 
the performance monitoring/breakpoint pins report performance events. Processor execution is not affected by 
reporting performance events.

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TR (trace message enable) flag (bit 6) — When set, trace messages are enabled as described in Section 
17.4.4, “Branch Trace Messages.” Setting this flag greatly reduces the performance of the processor. When 
trace messages are enabled, the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, 
and LastExceptionFromIP MSRs are undefined.

17.14.2  Last Branch and Last Exception MSRs

The LastBranchToIP and LastBranchFromIP MSRs are 32-bit registers for recording the instruction pointers for the 
last branch, interrupt, or exception that the processor took prior to a debug exception being generated. When a 
branch occurs, the processor loads the address of the branch instruction into the LastBranchFromIP MSR and loads 
the target address for the branch into the LastBranchToIP MSR. 
When an interrupt or exception occurs (other than a debug exception), the address of the instruction that was 
interrupted by the exception or interrupt is loaded into the LastBranchFromIP MSR and the address of the excep-
tion or interrupt handler that is called is loaded into the LastBranchToIP MSR.
The LastExceptionToIP and LastExceptionFromIP MSRs (also 32-bit registers) record the instruction pointers for 
the last branch that the processor took prior to an exception or interrupt being generated. When an exception or 
interrupt occurs, the contents of the LastBranchToIP and LastBranchFromIP MSRs are copied into these registers 
before the to and from addresses of the exception or interrupt are recorded in the LastBranchToIP and LastBranch-
FromIP MSRs.
These registers can be read using the RDMSR instruction.
Note that the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP 
MSRs are offsets into the current code segment, as opposed to linear addresses, which are saved in last branch 
records for the Pentium 4 and Intel Xeon processors.

17.14.3  Monitoring Branches, Exceptions, and Interrupts

When the LBR flag in the DEBUGCTLMSR register is set, the processor automatically begins recording branches 
that it takes, exceptions that are generated (except for debug exceptions), and interrupts that are serviced. Each 
time a branch, exception, or interrupt occurs, the processor records the to and from instruction pointers in the 
LastBranchToIP and LastBranchFromIP MSRs. In addition, for interrupts and exceptions, the processor copies the 
contents of the LastBranchToIP and LastBranchFromIP MSRs into the LastExceptionToIP and LastExceptionFromIP 
MSRs prior to recording the to and from addresses of the interrupt or exception.

Figure 17-18.  DEBUGCTLMSR Register (P6 Family Processors)

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TR — Trace messages enable
PBi — Performance monitoring/breakpoint pins
BTF — Single-step on branches
LBR — Last branch/interrupt/exception

7 6 5 4 3 2 1 0

P
B
2

P
B
1

P
B
0

B

T
F

T
R

L

B
R

P
B
3

Reserved