A-2 Vol. 3D

VMX CAPABILITY REPORTING FACILITY

If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it can 
configure the paging structures to map them into the linear-address space. If it does so, it should establish 
mappings that use the memory type reported in this MSR.

1

•

If bit 54 is read as 1, the logical processor reports information in the VM-exit instruction-information field on 
VM exits due to execution of the INS and OUTS instructions. This reporting is done only if this bit is read as 1.

•

Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See Appendix A.2 for details. It also 
reports support for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, 
IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and IA32_VMX_TRUE_ENTRY_CTLS. See 
Appendix A.3.1, Appendix A.3.2, Appendix A.4, and Appendix A.5 for details.

•

The values of bits 47:45 and bits 63:56 are reserved and are read as 0.

A.2 

RESERVED CONTROLS AND DEFAULT SETTINGS

As noted in Chapter 26, “VM Entries”, certain VMX controls are reserved and must be set to a specific value (0 or 1) 
determined by the processor. The specific value to which a reserved control must be set is its default setting. 
Software can discover the default setting of a reserved control by consulting the appropriate VMX capability MSR 
(see Appendix A.3 through Appendix A.5).
Future processors may define new functionality for one or more reserved controls. Such processors would allow 
each newly defined control to be set either to 0 or to 1. Software that does not desire a control’s new functionality 
should set the control to its default setting. For that reason, it is useful for software to know the default settings of 
the reserved controls.
Default settings partition the various controls into the following classes:

•

Always-flexible. These have never been reserved.

•

Default0. These are (or have been) reserved with a default setting of 0.

•

Default1. They are (or have been) reserved with a default setting of 1.

As noted in Appendix A.1, a logical processor uses bit 55 of the IA32_VMX_BASIC MSR to indicate whether any of 
the default1 controls may be 0:

•

If bit 55 of the IA32_VMX_BASIC MSR is read as 0, all the default1 controls are reserved and must be 1. 
VM entry will fail if any of these controls are 0 (see Section 26.2.1).

•

If bit 55 of the IA32_VMX_BASIC MSR is read as 1, not all the default1 controls are reserved, and some (but 
not necessarily all) may be 0. The CPU supports four (4) new VMX capability MSRs: 
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and 
IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3 through Appendix A.5 for details. (These MSRs are not 
supported if bit 55 of the IA32_VMX_BASIC MSR is read as 0.)

See Section 31.5.1 for recommended software algorithms for proper capability detection of the default1 controls.

A.3 VM-EXECUTION 

CONTROLS

There are separate capability MSRs for the pin-based VM-execution controls, the primary processor-based VM-
execution controls, and the secondary processor-based VM-execution controls. These are described in Appendix 
A.3.1, Appendix A.3.2, and Appendix A.3.3, respectively.

1. Alternatively, software may map any of these regions or structures with the UC memory type. (This may be necessary for the MSEG 

header.) Doing so is discouraged unless necessary as it will cause the performance of software accesses to those structures to suf-

fer. The processor will continue to use the memory type reported in the VMX capability MSR IA32_VMX_BASIC with the exceptions 

noted.