26-18 Vol. 3C
VM ENTRIES
•
An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entry would cause a general-protection
exception if executed via WRMSR with CPL = 0.
1
The VM entry fails if processing fails for any entry. The logical processor responds to such failures by loading state
from the host-state area, as it would for a VM exit. See Section 26.7.
If any MSR is being loaded in such a way that would architecturally require a TLB flush, the TLBs are updated so
that, after VM entry, the logical processor will not use any translations that were cached before the transition.
26.5 EVENT
INJECTION
If the valid bit in the VM-entry interruption-information field (see Section 24.8.3) is 1, VM entry causes an event to
be delivered (or made pending) after all components of guest state have been loaded (including MSRs) and after
the VM-execution control fields have been established.
•
If the interruption type in the field is 0 (external interrupt), 2 (non-maskable interrupt); 3 (hardware
exception), 4 (software interrupt), 5 (privileged software exception), or 6 (software exception), the event is
delivered as described in Section 26.5.1.
•
If the interruption type in the field is 7 (other event) and the vector field is 0, an MTF VM exit is pending after
VM entry. See Section 26.5.2.
26.5.1 Vectored-Event
Injection
VM entry delivers an injected vectored event within the guest context established by VM entry. This means that
delivery occurs after all components of guest state have been loaded (including MSRs) and after the VM-execution
control fields have been established.
2
The event is delivered using the vector in that field to select a descriptor in
the IDT. Since event injection occurs after loading IDTR from the guest-state area, this is the guest IDT.
Section 26.5.1.1 provides details of vectored-event injection. In general, the event is delivered exactly as if it had
been generated normally.
If event delivery encounters a nested exception (for example, a general-protection exception because the vector
indicates a descriptor beyond the IDT limit), the exception bitmap is consulted using the vector of that exception:
•
If the bit for the nested exception is 0, the nested exception is delivered normally. If the nested exception is
benign, it is delivered through the IDT. If it is contributory or a page fault, a double fault may be generated,
depending on the nature of the event whose delivery encountered the nested exception. See Chapter 6,
“Interrupt 8—Double Fault Exception (#DF)” in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
3
•
If the bit for the nested exception is 1, a VM exit occurs. Section 26.5.1.2 details cases in which event injection
causes a VM exit.
26.5.1.1 Details of Vectored-Event Injection
The event-injection process is controlled by the contents of the VM-entry interruption information field (format
given in Table 24-13), the VM-entry exception error-code field, and the VM-entry instruction-length field. The
following items provide details of the process:
1. If CR0.PG = 1, WRMSR to the IA32_EFER MSR causes a general-protection exception if it would modify the LME bit. If VM entry has
established CR0.PG = 1, the IA32_EFER MSR should not be included in the VM-entry MSR-load area for the purpose of modifying the
LME bit.
2. This does not imply that injection of an exception or interrupt will cause a VM exit due to the settings of VM-execution control fields
(such as the exception bitmap) that would cause a VM exit if the event had occurred in VMX non-root operation. In contrast, a nested
exception encountered during event delivery may cause a VM exit; see Section 26.5.1.1.
3. Hardware exceptions with the following unused vectors are considered benign: 15 and 21–31. A hardware exception with vector 20
is considered benign unless the processor supports the 1-setting of the “EPT-violation #VE” VM-execution control; in that case, it
has the same severity as page faults.