Vol. 3C 28-1

CHAPTER 28

VMX SUPPORT FOR ADDRESS TRANSLATION

The architecture for VMX operation includes two features that support address translation: virtual-processor iden-
tifiers (VPIDs) and the extended page-table mechanism (EPT). VPIDs are a mechanism for managing translations 
of linear addresses. EPT defines a layer of address translation that augments the translation of linear addresses.
Section 28.1 details the architecture of VPIDs. Section 28.2 provides the details of EPT. Section 28.3 explains how 
a logical processor may cache information from the paging structures, how it may use that cached information, and 
how software can managed the cached information.

28.1 

VIRTUAL PROCESSOR IDENTIFIERS (VPIDS)

The original architecture for VMX operation required VMX transitions to flush the TLBs and paging-structure caches. 
This ensured that translations cached for the old linear-address space would not be used after the transition.
Virtual-processor identifiers (VPIDs) introduce to VMX operation a facility by which a logical processor may cache 
information for multiple linear-address spaces. When VPIDs are used, VMX transitions may retain cached informa-
tion and the logical processor switches to a different linear-address space.
Section 28.3 details the mechanisms by which a logical processor manages information cached for multiple address 
spaces. A logical processor may tag some cached information with a 16-bit VPID. This section specifies how the 
current VPID is determined at any point in time:

•

The current VPID is 0000H in the following situations:
— Outside VMX operation. (This includes operation in system-management mode under the default treatment 

of SMIs and SMM with VMX operation; see Section 34.14.)

— In VMX root operation.
— In VMX non-root operation when the “enable VPID” VM-execution control is 0.

•

If the logical processor is in VMX non-root operation and the “enable VPID” VM-execution control is 1, the 
current VPID is the value of the VPID VM-execution control field in the VMCS. (VM entry ensures that this value 
is never 0000H; see Section 26.2.1.1.)

VPIDs and PCIDs (see Section 4.10.1) can be used concurrently. When this is done, the processor associates 
cached information with both a VPID and a PCID. Such information is used only if the current VPID and PCID both 
match those associated with the cached information.

28.2 

THE EXTENDED PAGE TABLE MECHANISM (EPT)

The extended page-table mechanism (EPT) is a feature that can be used to support the virtualization of physical 
memory. When EPT is in use, certain addresses that would normally be treated as physical addresses (and used to 
access memory) are instead treated as guest-physical addresses. Guest-physical addresses are translated by 
traversing a set of EPT paging structures to produce physical addresses that are used to access memory.

•

Section 28.2.1 gives an overview of EPT.

•

Section 28.2.2 describes operation of EPT-based address translation.

•

Section 28.2.3 discusses VM exits that may be caused by EPT.

•

Section 28.2.6 describes interactions between EPT and memory typing.

28.2.1 EPT 

Overview

EPT is used when the “enable EPT” VM-execution control is 1.

1

 It translates the guest-physical addresses used in 

VMX non-root operation and those used by VM entry for event injection.