33-6 Vol. 3C

HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITOR

33.3.2.4   I/O APIC Virtualization

The I/O APIC registers are typically mapped to a 1 MByte region where each I/O APIC is allocated a 4K address 
window within this range. The VMM may utilize physical memory virtualization to trap guest accesses to the virtual 
I/O APIC memory-mapped registers. The I/O APIC virtualization needs to emulate the various I/O APIC operations 
and registers such as identification/version registers, indirect-I/O-access registers, EOI register, and the I/O redi-
rection table. I/O APIC virtualization also need to emulate various redirection table entry settings such as delivery 
mode, destination mode, delivery status, polarity, masking, and trigger mode programmed by the guest and track 
remote-IRR state on guest EOI writes to various virtual local APICs.

33.3.2.5   Virtualization of Message Signaled Interrupts

The PCI Local Bus Specification (Rev. 2.2) introduces the concept of message signaled interrupts (MSI). MSI enable 
PCI devices to request service by writing a system-specified message to a system specified address. The transac-
tion address specifies the message destination while the transaction data specifies the interrupt vector, trigger 
mode and delivery mode. System software is expected to configure the message data and address during MSI 
device configuration, allocating one or more no-shared messages to MSI capable devices. Chapter 10, “Advanced 
Programmable Interrupt Controller (APIC),” specifies the MSI message address and data register formats to be 
followed on Intel 64 and IA-32 platforms. While MSI is optional for conventional PCI devices, it is the preferred 
interrupt mechanism for PCI-Express devices. 
Since the MSI address and data are configured through PCI configuration space, to control these physical interrupts 
the VMM needs to assume ownership of PCI configuration space. This allows the VMM to capture the guest config-
uration of message address and data for MSI-capable virtual and assigned guest devices. PCI configuration trans-
actions on PC-compatible systems are generated by software through two different methods: 
1. The standard CONFIG_ADDRESS/CONFIG_DATA register mechanism (CFCH/CF8H ports) as defined in the PCI 

Local Bus Specification.

2. The enhanced flat memory-mapped (MEMCFG) configuration mechanism as defined in the PCI-Express Base 

Specification (Rev. 1.0a.). 

The CFCH/CF8H configuration access from guests can be trapped by the VMM through use of I/O-bitmap VM-
execution controls. The memory-mapped PCI-Express MEMCFG guest configuration accesses can be trapped by 
VMM through physical memory virtualization.

33.3.3 

Examples of Handling of External Interrupts

The following sections illustrate interrupt processing in a VMM (when used to support the external interrupt virtu-
alization requirements). 

33.3.3.1   Guest Setup

The VMM sets up the guest to cause a VM exit to the VMM on external interrupts. This is done by setting the 
“external-interrupt exiting” VM-execution control in the guest controlling-VMCS. 

33.3.3.2   Processor Treatment of External Interrupt

Interrupts are automatically masked by hardware in the processor on VM exit by clearing RFLAGS.IF. The exit-
reason field in VMCS is set to 1 to indicate an external interrupt as the exit reason. 
If the VMM is utilizing the acknowledge-on-exit feature (by setting the “acknowledge interrupt on exit” VM-exit 
control), the processor acknowledges the interrupt, retrieves the host vector, and saves the interrupt in the VM-
exit-interruption-information field (in the VM-exit information region of the VMCS) before transitioning control to 
the VMM.