10-12 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10.5.1
Local Vector Table
The local vector table (LVT) allows software to specify the manner in which the local interrupts are delivered to the
processor core. It consists of the following 32-bit APIC registers (see Figure 10-8), one for each local interrupt:
•
LVT CMCI Register (FEE0 02F0H) — Specifies interrupt delivery when an overflow condition of corrected
machine check error count reaching a threshold value occurred in a machine check bank supporting CMCI (see
Section 15.5.1, “CMCI Local APIC Interface”).
•
LVT Timer Register (FEE0 0320H) — Specifies interrupt delivery when the APIC timer signals an interrupt
(see Section 10.5.4, “APIC Timer”).
•
LVT Thermal Monitor Register (FEE0 0330H) — Specifies interrupt delivery when the thermal sensor
generates an interrupt (see Section 14.7.2, “Thermal Monitor”). This LVT entry is implementation specific, not
architectural. If implemented, it will always be at base address FEE0 0330H.
•
LVT Performance Counter Register (FEE0 0340H) — Specifies interrupt delivery when a performance
counter generates an interrupt on overflow (see Section 18.15.5.8, “Generating an Interrupt on Overflow”).
This LVT entry is implementation specific, not architectural. If implemented, it is not guaranteed to be at base
address FEE0 0340H.
•
LVT LINT0 Register (FEE0 0350H) — Specifies interrupt delivery when an interrupt is signaled at the LINT0
pin.
•
LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when an interrupt is signaled at the LINT1
pin.
•
LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when the APIC detects an internal error
(see Section 10.5.3, “Error Handling”).
The LVT performance counter register and its associated interrupt were introduced in the P6 processors and are
also present in the Pentium 4 and Intel Xeon processors. The LVT thermal monitor register and its associated inter-
rupt were introduced in the Pentium 4 and Intel Xeon processors. The LVT CMCI register and its associated inter-
rupt were introduced in the Intel Xeon 5500 processors.
As shown in Figures 10-8, some of these fields and flags are not available (and reserved) for some entries.
The setup information that can be specified in the registers of the LVT table is as follows:
Vector
Interrupt vector number.
Delivery Mode
Specifies the type of interrupt to be sent to the processor. Some delivery modes will only
operate as intended when used in conjunction with a specific trigger mode. The allowable
delivery modes are as follows:
000 (Fixed)
Delivers the interrupt specified in the vector field.
010 (SMI)
Delivers an SMI interrupt to the processor core through the processor’s lo-
cal SMI signal path. When using this delivery mode, the vector field should
be set to 00H for future compatibility.
100 (NMI)
Delivers an NMI interrupt to the processor. The vector information is ig-
nored.
101 (INIT)
Delivers an INIT request to the processor core, which causes the processor
to perform an INIT. When using this delivery mode, the vector field should
be set to 00H for future compatibility. Not supported for the LVT CMCI reg-
ister, the LVT thermal monitor register, or the LVT performance counter
register.
110
Reserved; not supported for any LVT register.
111 (ExtINT) Causes the processor to respond to the interrupt as if the interrupt origi-
nated in an externally connected (8259A-compatible) interrupt controller.
A special INTA bus cycle corresponding to ExtINT, is routed to the external
controller. The external controller is expected to supply the vector informa-
tion. The APIC architecture supports only one ExtINT source in a system,
usually contained in the compatibility bridge. Only one processor in the
system should have an LVT entry configured to use the ExtINT delivery