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Vol. 3A 8-17




The Intel 64 and IA-32 architectures define several serializing instructions. These instructions force the 
processor to complete all modifications to flags, registers, and memory by previous instructions and to drain all 
buffered writes to memory before the next instruction is fetched and executed. For example, when a MOV to 
control register instruction is used to load a new value into control register CR0 to enable protected mode, the 
processor must perform a serializing operation before it enters protected mode. This serializing operation ensures 
that all operations that were started while the processor was in real-address mode are completed before the switch 
to protected mode is made.
The concept of serializing instructions was introduced into the IA-32 architecture with the Pentium processor to 
support parallel instruction execution. Serializing instructions have no meaning for the Intel486 and earlier proces-
sors that do not implement parallel instruction execution.
It is important to note that executing of serializing instructions on P6 and more recent processor families constrain 
speculative execution because the results of speculatively executed instructions are discarded. The following 
instructions are serializing instructions:

Privileged serializing instructions — INVD, INVEPT, INVLPG, INVVPID, LGDT, LIDT, LLDT, LTR, MOV (to 
control register, with the exception of MOV CR8


), MOV (to debug register), WBINVD, and WRMSR



Non-privileged serializing instructions — CPUID, IRET, and RSM.

When the processor serializes instruction execution, it ensures that all pending memory transactions are 
completed (including writes stored in its store buffer) before it executes the next  instruction. Nothing can pass a 
serializing instruction and a serializing instruction cannot pass any other instruction (read, write, instruction fetch, 
or I/O). For example, CPUID can be executed at any privilege level to serialize instruction execution with no effect 
on program flow, except that the EAX, EBX, ECX, and EDX registers are modified.
The following instructions are memory-ordering instructions, not serializing instructions. These drain the data 
memory subsystem. They do not serialize the instruction execution stream:


Non-privileged memory-ordering instructions — SFENCE, LFENCE, and MFENCE.

The SFENCE, LFENCE, and MFENCE instructions provide more granularity in controlling the serialization of memory 
loads and stores (see Section 8.2.5, “Strengthening or Weakening the Memory-Ordering Model”).
The following additional information is worth noting regarding serializing instructions:

The processor does not write back the contents of modified data in its data cache to external memory when it 
serializes instruction execution. Software can force modified data to be written back by executing the WBINVD 
instruction, which is a serializing instruction. The amount of time or cycles for WBINVD to complete will vary 
due to the size of different cache hierarchies and other factors. As a consequence, the use of the WBINVD 
instruction can have an impact on interrupt/event response time.

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register 
CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is 
fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction 
itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require 
the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, 
Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards 
and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump 
operation be performed.

Whenever an instruction is executed to change the contents of CR3 while paging is enabled, the next 
instruction is fetched using the translation tables that correspond to the new value of CR3. Therefore the next 
instruction and the sequentially following instructions should have a mapping based upon the new value of 
CR3. (Global entries in the TLBs are not invalidated, see Section 4.10.4, “Invalidation of TLBs and Paging-
Structure Caches.”

3. MOV CR8 is not defined architecturally as a serializing instruction.
4. WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.
5. LFENCE does provide some guarantees on instruction ordering. It does not execute until all prior instructions have completed locally, 

and no later instruction begins execution until LFENCE completes.