Vol. 3B 18-93

PERFORMANCE MONITORING

18.15.5.6   Cascading Counters

As described in Section 18.15.2, “Performance Counters,” eighteen performance counters are implemented in 
pairs. Nine pairs of counters and associated CCCRs are further organized as four blocks: BPU, MS, FLAME, and IQ 
(see Table 18-63). The first three blocks contain two pairs each. The IQ block contains three pairs of counters (12 
through 17) with associated CCCRs (MSR_IQ_CCCR0 through MSR_IQ_CCCR5).
The first 8 counter pairs (0 through 15) can be programmed using ESCRs to detect performance monitoring events. 
Pairs of ESCRs in each of the four blocks allow many different types of events to be counted. The cascade flag in 
the CCCR MSR allows nested monitoring of events to be performed by cascading one counter to a second counter 
located in another pair in the same block (see Figure 18-45 for the location of the flag).
Counters 0 and 1 form the first pair in the BPU block. Either counter 0 or 1 can be programmed to detect an event 
via MSR_MO B_ESCR0. Counters 0 and 2 can be cascaded in any order, as can counters 1 and 3. It’s possible to set 
up 4 counters in the same block to cascade on two pairs of independent events. The pairing described also applies 
to subsequent blocks. Since the IQ PUB has two extra counters, cascading operates somewhat differently if 16 and 
17 are involved. In the IQ block, counter 16 can only be cascaded from counter 14 (not from 12); counter 14 
cannot be cascaded from counter 16 using the CCCR cascade bit mechanism. Similar restrictions apply to counter 
17.

Example 18-1.  Counting Events

Assume a scenario where counter X is set up to count 200 occurrences of event A; then counter Y is set up to count 
400 occurrences of event B. Each counter is set up to count a specific event and overflow to the next counter. In 
the above example, counter X is preset for a count of -200 and counter Y for a count of -400; this setup causes the 
counters to overflow on the 200th and 400th counts respectively.
Continuing this scenario, counter X is set up to count indefinitely and wraparound on overflow. This is described in 
the basic performance counter setup procedure that begins in Section 18.15.5.1, “Selecting Events to Count.” 
Counter Y is set up with the cascade flag in its associated CCCR MSR set to 1 and its enable flag set to 0.
To begin the nested counting, the enable bit for the counter X is set. Once enabled, counter X counts until it over-
flows. At this point, counter Y is automatically enabled and begins counting. Thus counter X overflows after 200 
occurrences of event A. Counter Y then starts, counting 400 occurrences of event B before overflowing. When 
performance counters are cascaded, the counter Y would typically be set up to generate an interrupt on overflow. 
This is described in Section 18.15.5.8, “Generating an Interrupt on Overflow.” 
The cascading counters mechanism can be used to count a single event. The counting begins on one counter then 
continues on the second counter after the first counter overflows. This technique doubles the number of event 
counts that can be recorded, since the contents of the two counters can be added together.