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Vol. 3C 35-57

MODEL-SPECIFIC REGISTERS (MSRS)

35.3 

MSRS IN THE 45 NM AND 32 NM INTEL

®

 ATOM

™ 

PROCESSOR FAMILY

Table 35-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR 
addresses are also included in Table 35-4. These processors have a CPUID signature with 
DisplayFamily_DisplayModel of 06_1CH, 06_26H, 06_27H, 06_35H and 06_36H; see Table 35-1. 
The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel 
Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR 
governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation 
of both logical processors in the same core.

C000_

0101H

IA32_GS_BASE

Unique

Map of BASE Address of GS (R/W)
See Table 35-2.

C000_

0102H

IA32_KERNEL_GSBASE

Unique

Swap Target of BASE Address of GS (R/W) See Table 35-2.

Table 35-4.  MSRs in 45 nm and 32 nm Intel® Atom™ Processor Family

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec

0H

0

IA32_P5_MC_ADDR

Shared

See Section 35.22, “MSRs in Pentium Processors.”

1H

1

IA32_P5_MC_TYPE

Shared

See Section 35.22, “MSRs in Pentium Processors.”

6H

6

IA32_MONITOR_FILTER_

SIZE

Unique

See Section 8.10.5, “Monitor/Mwait Address Range Determination.” 

andTable 35-2

10H

16

IA32_TIME_STAMP_

COUNTER

Unique

See Section 17.15, “Time-Stamp Counter,” and see Table 35-2.

17H

23

IA32_PLATFORM_ID

Shared

Platform ID (R) 

See Table 35-2.

17H

23

MSR_PLATFORM_ID

Shared

Model Specific Platform ID (R) 

7:0

Reserved.

12:8

Maximum Qualified Ratio (R) 
The maximum allowed bus ratio.

63:13

Reserved.

1BH

27

IA32_APIC_BASE

Unique

See Section 10.4.4, “Local APIC Status and Location,” and 

Table 35-2.

2AH

42

MSR_EBL_CR_POWERON

Shared

Processor Hard Power-On Configuration (R/W) Enables and 

disables processor features; 
(R) indicates current processor configuration.

0

Reserved.

Table 35-3.  MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Register 

Address

Register Name

Shared/

Unique

Bit Description

 Hex

Dec