18-34 Vol. 3B

PERFORMANCE MONITORING

To specify a complete offcore response filter, software must properly program bits in the request and response type 
fields. A valid request type must have at least one bit set in the non-reserved bits of 15:0. A valid response type 
must be a non-zero value of the following expression:
[ANY ‘OR’ (L2 Hit) ] ‘XOR’ ( Snoop Info Bits) ‘XOR’ (Avg Latency)

18.7.3 

Average Offcore Request Latency Measurement

In Goldmont microarachitecture, measurement of average latency of offcore transaction requests is the same as 
described in Section 18.6.3.

18.8 

PERFORMANCE MONITORING FOR PROCESSORS BASED ON INTEL

® 

MICROARCHITECTURE CODE NAME NEHALEM

Intel Core i7 processor family

2

 supports architectural performance monitoring capability with version ID 3 (see 

Section 18.2.3) and a host of non-architectural monitoring capabilities. The Intel Core i7 processor family is based 
on Intel

®

 microarchitecture code name Nehalem, and provides four general-purpose performance counters 

(IA32_PMC0, IA32_PMC1, IA32_PMC2, IA32_PMC3) and three fixed-function performance counters 
(IA32_FIXED_CTR0, IA32_FIXED_CTR1, IA32_FIXED_CTR2) in the processor core. 
Non-architectural performance monitoring in Intel Core i7 processor family uses the IA32_PERFEVTSELx MSR to 
configure a set of non-architecture performance monitoring events to be counted by the corresponding general-
purpose performance counter. The list of non-architectural performance monitoring events is listed in Table 19-26. 
Non-architectural performance monitoring events fall into two broad categories:

•

Performance monitoring events in the processor core: These include many events that are similar to 
performance monitoring events available to processor based on Intel Core microarchitecture. Additionally, 
there are several enhancements in the performance monitoring capability for detecting microarchitectural 
conditions in the processor core or in the interaction of the processor core to the off-core sub-systems in the 
physical processor package. The off-core sub-systems in the physical processor package is loosely referred to 
as “uncore“.

•

Performance monitoring events in the uncore: The uncore sub-system is shared by more than one processor 
cores in the physical processor package. It provides additional performance monitoring facility outside of 
IA32_PMCx and performance monitoring events that are specific to the uncore sub-system.

Architectural and non-architectural performance monitoring events in Intel Core i7 processor family support thread 
qualification using bit 21 of IA32_PERFEVTSELx MSR. 
The bit fields within each IA32_PERFEVTSELx MSR are defined in Figure 18-6 and described in Section 18.2.1.1 and 
Section 18.2.3. 

NOTES:

1. See Section 18.6.3, “Average Offcore Request Latency Measurement” for details on how to use this bit to extract average latency.

2. Intel Xeon processor 5500 series and 3400 series are also based on Intel microarchitecture code name Nehalem, so the perfor-

mance monitoring facilities described in this section generally also apply.