34-2 Vol. 3C

SYSTEM MANAGEMENT MODE

A virtual machine monitor (VMM) using VMX can act as a host to multiple virtual machines and each virtual machine 
can support its own software stack of executive and application software. On processors that support VMX, virtual-
machine extensions may use system-management interrupts (SMIs) and system-management mode (SMM) in one 
of two ways:

•

Default treatment. System firmware handles SMIs. The processor saves architectural states and critical 
states relevant to VMX operation upon entering SMM. When the firmware completes servicing SMIs, it uses 
RSM to resume VMX operation.

•

Dual-monitor treatment. Two VM monitors collaborate to control the servicing of SMIs: one VMM operates 
outside of SMM to provide basic virtualization in support for guests; the other VMM operates inside SMM (while 
in VMX operation) to support system-management functions. The former is referred to as executive monitor, 
the latter SMM-transfer monitor (STM).

1

The default treatment is described in Section 34.14, “Default Treatment of SMIs and SMM with VMX Operation and 
SMX Operation”. Dual-monitor treatment of SMM is described in Section 34.15, “Dual-Monitor Treatment of SMIs 
and SMM”.

34.2 

SYSTEM MANAGEMENT INTERRUPT (SMI)

The only way to enter SMM is by signaling an SMI through the SMI# pin on the processor or through an SMI 
message received through the APIC bus. The SMI is a nonmaskable external interrupt that operates independently 
from the processor’s interrupt- and exception-handling mechanism and the local APIC. The SMI takes precedence 
over an NMI and a maskable interrupt. SMM is non-reentrant; that is, the SMI is disabled while the processor is in 
SMM.

NOTES

In the Pentium 4, Intel Xeon, and P6 family processors, when a processor that is designated as an 
application processor during an MP initialization sequence is waiting for a startup IPI (SIPI), it is in 
a mode where SMIs are masked. However if a SMI is received while an application processor is in 
the wait for SIPI mode, the SMI will be pended. The processor then responds on receipt of a SIPI by 
immediately servicing the pended SMI and going into SMM before handling the SIPI.
An SMI may be blocked for one instruction following execution of STI, MOV to SS, or POP into SS.

34.3 

SWITCHING BETWEEN SMM AND THE OTHER 

PROCESSOR OPERATING MODES

Figure 2-3 shows how the processor moves between SMM and the other processor operating modes (protected, 
real-address, and virtual-8086). Signaling an SMI while the processor is in real-address, protected, or virtual-8086 
modes always causes the processor to switch to SMM. Upon execution of the RSM instruction, the processor always 
returns to the mode it was in when the SMI occurred. 

34.3.1 Entering 

SMM

The processor always handles an SMI on an architecturally defined “interruptible” point in program execution 
(which is commonly at an IA-32 architecture instruction boundary). When the processor receives an SMI, it waits 
for all instructions to retire and for all stores to complete. The processor then saves its current context in SMRAM 
(see Section 34.4), enters SMM, and begins to execute the SMI handler.
Upon entering SMM, the processor signals external hardware that SMI handling has begun. The signaling mecha-
nism used is implementation dependent. For the P6 family processors, an SMI acknowledge transaction is gener-

1. The dual-monitor treatment may not be supported by all processors. Software should consult the VMX capability MSR 

IA32_VMX_BASIC (see Appendix A.1) to determine whether it is supported.