31-14 Vol. 3C

VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS

In addition to the steps outlined in Section 31.6, VMM writers need to: 

•

Set the “IA-32e-mode guest” VM-entry control to 1 in the VMCS to assure VM-entry (VMLAUNCH or 
VMRESUME) will establish a 64-bit (or 32-bit compatible) guest operating environment. 

•

Enable paging (CR0.PG) and PAE mode (CR4.PAE) to assure VM-entry to a 64-bit guest will succeed. 

•

Ensure that the host to be in IA-32e mode (the IA32_EFER.LMA must be set to 1) and the setting of the VM-exit 
“host address-space size” control bit in the VMCS must also be set to 1. 

If each of the above conditions holds true, then VM-entry will copy the value of the VM-entry “IA-32e-mode guest” 
control bit into the guests IA32_EFER.LME bit, which will result in subsequent activation of IA-32e mode. If any of 
the above conditions is false, the VM-entry will fail and load state from the host-state area of the working VMCS as 
if a VM exit had occurred (see Section 26.7).
The following VMCS controls determine the value of IA32_EFER on a VM entry: the “IA-32e-mode guest” VM-entry 
control (described above), the “load IA32_EFER” VM-entry control, the “VM-entry MSR-load count,” and the “VM-
entry MSR-load address” (see Section 26.4).
If the “load IA32_EFER” VM-entry control is 1, the value of the LME and LMA bits in the IA32_EFER field in the 
guest-state area must be the value of the “IA-32e-mode guest” VM-entry control. Otherwise, the VM entry fails.
The loading of IA32_EFER.LME bit (described above) precedes any loading of the IA32_EFER MSR from the VM-
entry MSR-load area of the VMCS. If loading of IA32_EFER is specified in the VM-entry MSR-load area, the value of 
the LME bit in the load image should be match the setting of the “IA-32e-mode guest” VM-entry control. Otherwise, 
the attempt to modify the LME bit (while paging is enabled) results in a failed VM entry. However, IA32_EFER.LMA 
is always set by the processor to equal IA32_EFER.LME & CR0.PG; the value specified for LMA in the load image of 
the IA32_EFER MSR is ignored. For these and performance reasons, VMM writers may choose to not use the VM-
exit/entry MSR-load/save areas for IA32_EFER MSR.
Note that the VMM can control the processor’s architectural state when transferring control to a VM. VMM writers 
may choose to launch guests in protected mode and subsequently allow the guest to activate IA-32e mode or they 
may allow guests to toggle in and out of IA-32e mode. In this case, the VMM should require VM exit on accesses to 
the IA32_EFER MSR to detect changes in the operating mode and modify the VM-entry “IA-32e-mode guest” 
control accordingly.
A VMM should save/restore the extended (full 64-bit) contents of the guest general-purpose registers, the new 
general-purpose registers (R8-R15) and the SIMD registers introduced in 64-bit mode should it need to modify 
these upon VM exit. 

31.9.5 32-Bit 

Guests

To launch or resume a 32-bit guest, VMM writers can follow the steps outlined in Section 31.6, making sure that the 
“IA-32e-mode guest” VM-entry control bit is set to 0. Then the “IA-32e-mode guest” control bit is copied into the 
guest IA32_EFER.LME bit, establishing IA32_EFER.LMA as 0. 

31.10 HANDLING 

MODEL 

SPECIFIC REGISTERS

Model specific registers (MSR) provide a wide range of functionality. They affect processor features, control the 
programming interfaces, or are used in conjunction with specific instructions. As part of processor virtualization, a 
VMM may wish to protect some or all MSR resources from direct guest access. 
VMX operation provides the following features to virtualize processor MSRs.

31.10.1  Using VM-Execution Controls

Processor-based VM-execution controls provide two levels of support for handling guest access to processor MSRs 
using RDMSR and WRMSR:

•

MSR bitmaps: In VMX implementations that support a 1-setting (see Appendix A) of the user-MSR-bitmaps 
execution control bit, MSR bitmaps can be used to provide flexibility in managing guest MSR accesses. The