Vol. 3B 17-17

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

17.4.8.2   LBR Stack and IA-32 Processors 

The LBR MSRs in IA-32 processors introduced prior to Intel 64 architecture store the 32-bit “To Linear Address” and 
“From Linear Address“ using the high and low half of each 64-bit MSR. 

17.4.8.3   Last Exception Records and Intel 64 Architecture

Intel 64 and IA-32 processors also provide MSRs that store the branch record for the last branch taken prior to an 
exception or an interrupt. The location of the last exception record (LER) MSRs are model specific. The MSRs that 
store last exception records are 64-bits. If IA-32e mode is disabled, only the lower 32-bits of the address is 
recorded. If IA-32e mode is enabled, the processor writes 64-bit values into the MSR. In 64-bit mode, last excep-
tion records store 64-bit addresses; in compatibility mode, the upper 32-bits of last exception records are cleared.

17.4.9 

BTS and DS Save Area

The Debug store (DS) feature flag (bit 21), returned by CPUID.1:EDX[21] indicates that the processor provides 
the debug store (DS) mechanism. The DS mechanism allows: 

•

BTMs to be stored in a memory-resident BTS buffer. See Section 17.4.5, “Branch Trace Store (BTS).” 

•

Processor event-based sampling (PEBS) also uses the DS save area provided by debug store mechanism. The 
capability of PEBS varies across different microarchitectures. See Section 18.4.4, “Processor Event Based 
Sampling (PEBS),” and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, “Perfor-
mance Monitoring.”. 

When CPUID.1:EDX[21] is set:

•

The BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags in the IA32_MISC_ENABLE MSR indicate (when clear) 
the availability of the BTS and PEBS facilities, including the ability to set the BTS and BTINT bits in the 
appropriate DEBUGCTL MSR.

•

The IA32_DS_AREA MSR exists and points to the DS save area. 

The debug store (DS) save area is a software-designated area of memory that is used to collect the following two 
types of information:

•

Branch records — When the BTS flag in the IA32_DEBUGCTL MSR is set, a branch record is stored in the BTS 
buffer in the DS save area whenever a taken branch, interrupt, or exception is detected. 

•

PEBS records — When a performance counter is configured for PEBS, a PEBS record is stored in the PEBS 
buffer in the DS save area after the counter overflow occurs. This record contains the architectural state of the 
processor (state of the 8 general purpose registers, EIP register, and EFLAGS register) at the next occurrence 
of the PEBS event that caused the counter to overflow. When the state information has been logged, the 
counter is automatically reset to a specified value, and event counting begins again. The content layout of a 
PEBS record varies across different implementations that support PEBS. See Section 18.4.4.2 for details of 
enumerating PEBS record format.

NOTES

Prior to processors based on the Goldmont microarchitecture, PEBS facility only supports a subset 
of implementation-specific precise events. See Section 18.7.1 for a PEBS enhancement that can 
generate records for both precise and non-precise events.

The DS save area and recording mechanism are disabled on transition to system-management 
mode (SMM). Similarly, the recording mechanism is disabled on the generation of a machine-check 
exception and is cleared on processor RESET and INIT. DS recording is available in real-address 
mode.

The BTS and PEBS facilities may not be available on all processors. The availability of these facilities 
is indicated by the BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags, respectively, in the 
IA32_MISC_ENABLE MSR (see Chapter 35).