Vol. 3B 18-21
PERFORMANCE MONITORING
18.4.4.1 Setting up the PEBS Buffer
For processors based on Intel Core microarchitecture, PEBS is available using IA32_PMC0 only. Use the following
procedure to set up the processor and IA32_PMC0 counter for PEBS:
1. Set up the precise event buffering facilities. Place values in the precise event buffer base, precise event index,
precise event absolute maximum, precise event interrupt threshold, and precise event counter reset fields of
the DS buffer management area. In processors based on Intel Core microarchitecture, PEBS records consist of
64-bit address entries. See Figure 17-8 to set up the precise event records buffer in memory.
2. Enable PEBS. Set the Enable PEBS on PMC0 flag (bit 0) in IA32_PEBS_ENABLE MSR.
3. Set up the IA32_PMC0 performance counter and IA32_PERFEVTSEL0 for an event listed in Table 18-10.
18.4.4.2 PEBS Record Format
The PEBS record format may be extended across different processor implementations. The
IA32_PERF_CAPABILITES MSR defines a mechanism for software to handle the evolution of PEBS record format in
processors that support architectural performance monitoring with version id equals 2 or higher. The bit fields of
IA32_PERF_CAPABILITES are defined in Table 35-2 of Chapter 35, “Model-Specific Registers (MSRs)â€. The relevant
bit fields that governs PEBS are:
•
PEBSTrap [bit 6]: When set, PEBS recording is trap-like. After the PEBS-enabled counter has overflowed, PEBS
record is recorded for the next PEBS-able event at the completion of the sampled instruction causing the PEBS
event. When clear, PEBS recording is fault-like. The PEBS record is recorded before the sampled instruction
causing the PEBS event.
•
PEBSSaveArchRegs [bit 7]: When set, PEBS will save architectural register and state information according to
the encoded value of the PEBSRecordFormat field. When clear, only the return instruction pointer and flags are
recorded. On processors based on Intel Core microarchitecture, this bit is always 1
•
PEBSRecordFormat [bits 11:8]: Valid encodings are:
— 0000B: Only general-purpose registers, instruction pointer and RFLAGS registers are saved in each PEBS
record (seeSection 18.15.7).
— 0001B: PEBS record includes additional information of IA32_PERF_GLOBAL_STATUS and load latency data.
— 0010B: PEBS record includes additional information of IA32_PERF_GLOBAL_STATUS, load latency data,
and TSX tuning information. (seeSection 18.11.2).
— 0011B: PEBS record includes additional information of load latency data, TSX tuning information, TSC data,
and the applicable counter field replaces IA32_PERF_GLOBAL_STATUS at offset 90H. (see Section
18.13.1.1).
18.4.4.3 Writing a PEBS Interrupt Service Routine
The PEBS facilities share the same interrupt vector and interrupt service routine (called the DS ISR) with the Inter-
rupt-based event sampling and BTS facilities. To handle PEBS interrupts, PEBS handler code must be included in
the DS ISR. See Section 17.4.9.1, “64 Bit Format of the DS Save Area,†for guidelines when writing the DS ISR.
The service routine can query MSR_PERF_GLOBAL_STATUS to determine which counter(s) caused of overflow
condition. The service routine should clear overflow indicator by writing to MSR_PERF_GLOBAL_OVF_CTL.