17-14 Vol. 3B

DEBUG, BRANCH PROFILE, TSC, AND RESOURCE MONITORING FEATURES

17.4.6 

CPL-Qualified Branch Trace Mechanism

CPL-qualified branch trace mechanism is available to a subset of Intel 64 and IA-32 processors that support the 
branch trace storing mechanism. The processor supports the CPL-qualified branch trace mechanism if 
CPUID.01H:ECX[bit 4] = 1.
The CPL-qualified branch trace mechanism is described in Section 17.4.9.4. System software can selectively specify 
CPL qualification to not send/store Branch Trace Messages associated with a specified privilege level. Two bit fields, 
BTS_OFF_USR (bit 10) and BTS_OFF_OS (bit 9), are provided in the debug control register to specify the CPL of 
BTMs that will not be logged in the BTS buffer or sent on the bus.

17.4.7 

Freezing LBR and Performance Counters on PMI 

Many issues may generate a performance monitoring interrupt (PMI); a PMI service handler will need to determine 
cause to handle the situation. Two capabilities that allow a PMI service routine to improve branch tracing and 
performance monitoring are available for processors supporting architectural performance monitoring version 2 or 
greater (i.e. CPUID.0AH:EAX[7:0] > 1). These capabilities provides the following interface in IA32_DEBUGCTL to 
reduce runtime overhead of PMI servicing, profiler-contributed skew effects on analysis or counter metrics:

•

Freezing LBRs on PMI (bit 11)— Allows the PMI service routine to ensure the content in the LBR stack are 
associated with the target workload and not polluted by the branch flows of handling the PMI. Depending on the 
version ID enumerated by CPUID.0AH:EAX.ArchPerfMonVerID[bits 7:0], two flavors are supported:
— Legacy Freeze_LBR_on_PMI is supported for ArchPerfMonVerID <= 3 and ArchPerfMonVerID >1. If 

IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the LBR is frozen on the overflowed condition of the buffer 
area, the processor clears the LBR bit (bit 0) in IA32_DEBUGCTL. Software must then re-enable 
IA32_DEBUGCTL.LBR to resume recording branches. When using this feature, software should be careful 
about writes to IA32_DEBUGCTL to avoid re-enabling LBRs by accident if they were just disabled.

— Streamlined Freeze_LBR_on_PMI is supported for ArchPerfMonVerID >= 4. If 

IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the processor behaves as follows:

•

sets IA32_PERF_GLOBAL_STATUS.LBR_Frz =1 to disable recording, but does not change the LBR bit 

(bit 0) in IA32_DEBUGCTL. The LBRs are frozen on the overflowed condition of the buffer area.

•

Freezing PMCs on PMI (bit 12) — Allows the PMI service routine to ensure the content in the performance 
counters are associated with the target workload and not polluted by the PMI and activities within the PMI 
service routine. Depending on the version ID enumerated by CPUID.0AH:EAX.ArchPerfMonVerID[bits 7:0], two 
flavors are supported:
— Legacy Freeze_Perfmon_on_PMI is supported for ArchPerfMonVerID <= 3 and ArchPerfMonVerID >1. If 

IA32_DEBUGCTL.Freeze_Perfmon_On_PMI = 1, the performance counters are frozen on the counter 
overflowed condition when the processor clears the IA32_PERF_GLOBAL_CTRL MSR (see Figure 18-3). The 
PMCs affected include both general-purpose counters and fixed-function counters (see Section 18.4.1, 
“Fixed-function Performance Counters”). Software must re-enable counts by writing 1s to the corre-
sponding enable bits in IA32_PERF_GLOBAL_CTRL before leaving a PMI service routine to continue counter 
operation.

— Streamlined Freeze_Perfmon_on_PMI is supported for ArchPerfMonVerID >= 4. The processor behaves as 

follows:

•

sets IA32_PERF_GLOBAL_STATUS.CTR_Frz =1 to disable counting on a counter overflow condition, but 

does not change the IA32_PERF_GLOBAL_CTRL MSR. 

Freezing LBRs and PMCs on PMIs (both legacy and streamlined operation) occur when one of the following applies:

•

A performance counter had an overflow and was programmed to signal a PMI in case of an overflow.
— For the general-purpose counters; enabling PMI is done by setting bit 20 of the IA32_PERFEVTSELx 

register.

— For the fixed-function counters; enabling PMI is done by setting the 3rd bit in the corresponding 4-bit 

control field of the MSR_PERF_FIXED_CTR_CTRL register (see Figure 18-1) or IA32_FIXED_CTR_CTRL MSR 
(see Figure 18-2).

•

The PEBS buffer is almost full and reaches the interrupt threshold.