22-14 Vol. 3B
ARCHITECTURE COMPATIBILITY
22.18.7.14 FSETPM Instruction
With the 32-bit x87 FPUs, the FSETPM instruction is treated as NOP (no operation). This instruction informs the
Intel 287 math coprocessor that the processor is in protected mode. This change has no impact on existing soft-
ware. The 32-bit x87 FPUs handle all addressing and exception-pointer information, whether in protected mode or
not.
22.18.7.15 FXAM Instruction
With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing the FXAM instruction, it not
generate combinations of C0 through C3 equal to 1101 or 1111. The 16-bit IA-32 math coprocessors may generate
these combinations, among others. This difference has no impact on existing software; it provides a performance
upgrade to provide repeatable results.
22.18.7.16 FSAVE and FSTENV Instructions
With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE or FSTENV is undefined if the
previous floating-point instruction did not refer to memory
22.18.8 Transcendental
Instructions
The floating-point results of the P6 family and Pentium processors for transcendental instructions in the core range
may differ from the Intel486 processors by about 2 or 3 ulps (see “Transcendental Instruction Accuracy” in Chapter
8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Condition code flag C1 of the status word may differ as a result. The exact threshold for underflow and
overflow will vary by a few ulps. The P6 family and Pentium processors’ results will have a worst case error of less
than 1 ulp when rounding to the nearest-even and less than 1.5 ulps when rounding in other modes. The transcen-
dental instructions are guaranteed to be monotonic, with respect to the input operands, throughout the domain
supported by the instruction.
Transcendental instructions may generate different results in the round-up flag (C1) on the 32-bit x87 FPUs. The
round-up flag is undefined for these instructions on the 16-bit IA-32 math coprocessors. This difference has no
impact on existing software.
22.18.9 Obsolete
Instructions
The 8087 math coprocessor instructions FENI and FDISI and the Intel 287 math coprocessor instruction FSETPM
are treated as integer NOP instructions in the 32-bit x87 FPUs. If these opcodes are detected in the instruction
stream, no specific operation is performed and no internal states are affected.
22.18.10 WAIT/FWAIT Prefix Differences
On the Intel486 processor, when a WAIT/FWAIT instruction precedes a floating-point instruction (one which itself
automatically synchronizes with the previous floating-point instruction), the WAIT/FWAIT instruction is treated as
a no-op. Pending floating-point exceptions from a previous floating-point instruction are processed not on the
WAIT/FWAIT instruction but on the floating-point instruction following the WAIT/FWAIT instruction. In such a case,
the report of a floating-point exception may appear one instruction later on the Intel486 processor than on a P6
family or Pentium FPU, or on Intel 387 math coprocessor.
22.18.11 Operands Split Across Segments and/or Pages
On the P6 family, Pentium, and Intel486 processor FPUs, when the first half of an operand to be written is inside a
page or segment and the second half is outside, a memory fault can cause the first half to be stored but not the
second half. In this situation, the Intel 387 math coprocessor stores nothing.