Vol. 3A 6-37

INTERRUPT AND EXCEPTION HANDLING

Interrupt 13—General Protection Exception (#GP)

Exception Class

Fault.

Description

Indicates that the processor detected one of a class of protection violations called “general-protection violations.” 
The conditions that cause this exception to be generated comprise all the protection violations that do not cause 
other exceptions to be generated (such as, invalid-TSS, segment-not-present, stack-fault, or page-fault excep-
tions). The following conditions cause general-protection exceptions to be generated:

•

Exceeding the segment limit when accessing the CS, DS, ES, FS, or GS segments.

•

Exceeding the segment limit when referencing a descriptor table (except during a task switch or a stack 
switch).

•

Transferring execution to a segment that is not executable.

•

Writing to a code segment or a read-only data segment.

•

Reading from an execute-only code segment.

•

Loading the SS register with a segment selector for a read-only segment (unless the selector comes from a TSS 
during a task switch, in which case an invalid-TSS exception occurs).

•

Loading the SS, DS, ES, FS, or GS register with a segment selector for a system segment.

•

Loading the DS, ES, FS, or GS register with a segment selector for an execute-only code segment.

•

Loading the SS register with the segment selector of an executable segment or a null segment selector.

•

Loading the CS register with a segment selector for a data segment or a null segment selector.

•

Accessing memory using the DS, ES, FS, or GS register when it contains a null segment selector.

•

Switching to a busy task during a call or jump to a TSS.

•

Using a segment selector on a non-IRET task switch that points to a TSS descriptor in the current LDT. TSS 
descriptors can only reside in the GDT. This condition causes a #TS exception during an IRET task switch.

•

Violating any of the privilege rules described in Chapter 5, “Protection.”

•

Exceeding the instruction length limit of 15 bytes (this only can occur when redundant prefixes are placed 
before an instruction).

•

Loading the CR0 register with a set PG flag (paging enabled) and a clear PE flag (protection disabled).

•

Loading the CR0 register with a set NW flag and a clear CD flag.

•

Referencing an entry in the IDT (following an interrupt or exception) that is not an interrupt, trap, or task gate.

•

Attempting to access an interrupt or exception handler through an interrupt or trap gate from virtual-8086 
mode when the handler’s code segment DPL is greater than 0.

•

Attempting to write a 1 into a reserved bit of CR4.

•

Attempting to execute a privileged instruction when the CPL is not equal to 0 (see Section 5.9, “Privileged 
Instructions,” for a list of privileged instructions).

•

Attempting to execute SGDT, SIDT, SLDT, SMSW, or STR when CR4.UMIP = 1 and the CPL is not equal to 0.

•

Writing to a reserved bit in an MSR.

•

Accessing a gate that contains a null segment selector.

•

Executing the INT n instruction when the CPL is greater than the DPL of the referenced interrupt, trap, or task 
gate.

•

The segment selector in a call, interrupt, or trap gate does not point to a code segment.

•

The segment selector operand in the LLDT instruction is a local type (TI flag is set) or does not point to a 
segment descriptor of the LDT type.

•

The segment selector operand in the LTR instruction is local or points to a TSS that is not available.

•

The target code-segment selector for a call, jump, or return is null.